From: Senthil Balasubramanian Date: Wed, 10 Nov 2010 13:03:08 +0000 (-0800) Subject: ath9k_hw: Initialize 2GHz CTL properly. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ef5a6a7573b7a12ced67dae155be8a909bc245d6;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git ath9k_hw: Initialize 2GHz CTL properly. The last 2GHz CTL was not being initialized, so power was being set to 0 instead of 30dbm. Initialize to 30 like other CTLs. Signed-off-by: Senthil Balasubramanian Signed-off-by: John W. Linville --- diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index bc3f49c5c5b4..b33fb5bd8886 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -306,6 +306,7 @@ static const struct ar9300_eeprom ar9300_default = { { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, }, .modalHeader5G = { /* 4 idle,t1,t2,b (4 bits per setting) */