From: Youngmin Nam Date: Wed, 5 Dec 2018 05:09:12 +0000 (+0900) Subject: [RAMEN9610-9153][9610] soc: samsung: acpm: Add disable PMU_DBGCORE interrupt on ACPM... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ee9fe8e9a24c742e49c9df24f5a9671f412c2374;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [RAMEN9610-9153][9610] soc: samsung: acpm: Add disable PMU_DBGCORE interrupt on ACPM timeout Change-Id: I6f3425912b4cf29441a952cd40f9e154a8c394c6 Signed-off-by: Youngmin Nam --- diff --git a/drivers/soc/samsung/acpm/acpm_ipc.c b/drivers/soc/samsung/acpm/acpm_ipc.c index 85399028f734..e2d0239cb998 100644 --- a/drivers/soc/samsung/acpm/acpm_ipc.c +++ b/drivers/soc/samsung/acpm/acpm_ipc.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "acpm.h" #include "acpm_ipc.h" @@ -577,6 +578,30 @@ int acpm_ipc_send_data_sync(unsigned int channel_id, struct ipc_config *cfg) return ret; } +/* EXYNOS9610 PMU_DBGCORE */ +#define PMU_DBGCORE_INTR_ENABLE (0x430) +#define PMU_DBGCORE_INTR (0x434) + +/* PMU_DBGCORE BIT FIELD */ +#define CLUSTER0_WDTRESET_ENABLE (1 << 0) +#define WRESET_ENABLE (1 << 7) +#define INTR_ACK (1 << 31) + +void exynos9610_disable_pmu_dbg_intr(void) +{ + u32 reg; + + /* PMU_DBGCORE interrupt disable */ + exynos_pmu_read(PMU_DBGCORE_INTR_ENABLE, ®); + reg &= ~(CLUSTER0_WDTRESET_ENABLE | WRESET_ENABLE); + exynos_pmu_write(PMU_DBGCORE_INTR_ENABLE, reg); + + /* PMU_DBGCORE ack */ + exynos_pmu_read(PMU_DBGCORE_INTR, ®); + reg |= INTR_ACK; + exynos_pmu_write(PMU_DBGCORE_INTR, reg); +} + int acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg) { unsigned int front; @@ -685,6 +710,9 @@ retry: acpm_debug->debug_log_level = 0; acpm_ramdump(); + /* To prevent WARM reset stuck, HOST-AP set ACK bit */ + exynos9610_disable_pmu_dbg_intr(); + BUG_ON(timeout_flag); return -ETIMEDOUT; }