From: Linus Torvalds Date: Tue, 2 Jul 2013 21:23:01 +0000 (-0700) Subject: Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ee1a8d402e7e204d57fb108aa40003b6d1633036;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git Merge tag 'dt-for-linus' of git://git./linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits) ARM: at91: dt: rm9200ek: add spi support ARM: at91: dt: rm9200: add spi support ARM: at91/DT: at91sam9n12: add SPI DMA client infos ARM: at91/DT: sama5d3: add SPI DMA client infos ARM: at91/DT: fix SPI compatibility string ARM: Kirkwood: Fix the internal register ranges translation ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency ARM: dts: omap4-panda: Fix DVI EDID reads ARM: dts: omap4-panda: Add USB Host support arm: mvebu: enable mini-PCIe connectors on Armada 370 RD ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: dts: AM43x EPOS EVM support ARM: dts: OMAP5: Add bandgap DT entry ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ... --- ee1a8d402e7e204d57fb108aa40003b6d1633036 diff --cc arch/arm/boot/dts/armada-370-xp.dtsi index 52a1f5efc086,a679b6697a98..90b117624abb --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@@ -94,17 -103,17 +103,17 @@@ reg = <0x72004 0x4>; }; - ethernet@70000 { + eth0: ethernet@70000 { compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; + reg = <0x70000 0x4000>; interrupts = <8>; clocks = <&gateclk 4>; status = "disabled"; }; - ethernet@74000 { + eth1: ethernet@74000 { compatible = "marvell,armada-370-neta"; - reg = <0x74000 0x2500>; + reg = <0x74000 0x4000>; interrupts = <10>; clocks = <&gateclk 3>; status = "disabled"; diff --cc arch/arm/boot/dts/armada-xp-mv78460.dtsi index 488ca5eb9a55,386f0ce48453..c7b1f4d5c1c7 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@@ -105,9 -106,9 +106,9 @@@ interrupts = <91>; }; - ethernet@34000 { + eth3: ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --cc arch/arm/boot/dts/armada-xp.dtsi index 1ee8540b0eba,e481d54b565c..416eb9481844 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@@ -86,9 -90,9 +90,9 @@@ reg = <0x18200 0x500>; }; - ethernet@30000 { + eth2: ethernet@30000 { compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x2500>; + reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; diff --cc arch/arm/boot/dts/exynos5440.dtsi index b7ffc4dfe219,9589ed9282f1..bfcb907b7e33 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@@ -214,44 -205,29 +205,67 @@@ interrupts = <0 17 0>, <0 16 0>; clocks = <&clock 21>; clock-names = "rtc"; - status = "disabled"; + }; + + sata@210000 { + compatible = "snps,exynos5440-ahci"; + reg = <0x210000 0x10000>; + interrupts = <0 30 0>; + clocks = <&clock 23>; + clock-names = "sata"; + }; + + ohci@220000 { + compatible = "samsung,exynos5440-ohci"; + reg = <0x220000 0x1000>; + interrupts = <0 29 0>; + clocks = <&clock 24>; + clock-names = "usbhost"; + }; + + ehci@221000 { + compatible = "samsung,exynos5440-ehci"; + reg = <0x221000 0x1000>; + interrupts = <0 29 0>; + clocks = <&clock 24>; + clock-names = "usbhost"; }; + + pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + clocks = <&clock 28>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; + }; + + pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + clocks = <&clock 29>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; + }; }; diff --cc arch/arm/boot/dts/kirkwood-6281.dtsi index 51376683dbcd,0ed2f56a91f1..1e5bef0bead7 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@@ -41,35 -41,32 +41,63 @@@ }; }; + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; ++ + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; }; }; diff --cc arch/arm/boot/dts/kirkwood-mplcec4.dts index 90501cf129bb,211916a5a0fe..6179333fd71f --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@@ -136,17 -131,9 +131,17 @@@ pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 15 0>; + cd-gpios = <&gpio1 15 1>; /* No WP GPIO */ }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --cc arch/arm/boot/dts/kirkwood-ts219.dtsi index 09c820fc177f,b9325d45be78..0c9a94cd666c --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@@ -28,14 -34,13 +32,18 @@@ serial@12100 { clock-frequency = <200000000>; status = "okay"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; }; + poweroff@12100 { + compatible = "qnap,power-off"; + reg = <0x12000 0x100>; + clocks = <&gate_clk 7>; + }; spi@10600 { status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; diff --cc arch/arm/boot/dts/kirkwood.dtsi index 7eef88f00fea,1ae3eb2dea2e..9809fc1f105c --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@@ -18,8 -30,8 +30,9 @@@ ocp@f1000000 { compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x4000000 + ranges = <0x00000000 0xf1000000 0x0100000 + 0xe0000000 0xe0000000 0x8100000 /* PCIE */ + 0xf4000000 0xf4000000 0x0000400 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; diff --cc arch/arm/mach-mxs/mach-mxs.c index d67ecc1c8847,ba227cb2c93b..7fa611c1b287 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@@ -434,7 -544,7 +544,6 @@@ static const char *mxs_dt_compat[] __in }; DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") - .init_irq = irqchip_init, - .map_io = debug_ll_io_init, .handle_irq = icoll_handle_irq, .init_time = mxs_timer_init, .init_machine = mxs_machine_init, diff --cc arch/arm/mach-nomadik/cpu-8815.c index 46cce9baa129,89e2c03db178..2df209ed1a07 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@@ -25,10 -25,9 +25,8 @@@ #include #include #include -#include #include - #include - #include - #include + #include #include #include #include diff --cc arch/arm/mach-omap2/cclock33xx_data.c index 0346de56436c,a8140b6885e3..ba6534d7f155 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@@ -862,33 -858,42 +858,69 @@@ static struct clk_hw_omap wdt1_fck_hw DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); +static const char *pwmss_clk_parents[] = { + "dpll_per_m2_ck", +}; + +static const struct clk_ops ehrpwm_tbclk_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, +}; + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS0_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS1_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS2_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + + /* + * debugss optional clocks + */ + DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck, + 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL); + + DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck, + 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL); + + static const char *stm_pmd_clock_mux_ck_parents[] = { + "dbg_sysclk_ck", "dbg_clka_ck", + }; + + DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, + AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT, + AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL); + + DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, + AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_TRC_PMD_CLKSEL_SHIFT, + AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL); + + DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck", + &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_STM_PMD_CLKDIVSEL_SHIFT, + AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + + DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck", + &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + AM33XX_TRC_PMD_CLKDIVSEL_SHIFT, + AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + /* * clkdev */ @@@ -969,9 -973,13 +1000,16 @@@ static struct omap_clk am33xx_clks[] = CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), CLK(NULL, "timer_sys_ck", &sys_clkin_ck), + CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck), + CLK(NULL, "dbg_clka_ck", &dbg_clka_ck), + CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck), + CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), + CLK(NULL, "clkout2_ck", &clkout2_ck), + CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), + CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), + CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), };