From: David Daney Date: Thu, 11 Dec 2008 23:33:24 +0000 (-0800) Subject: MIPS: Add Cavium OCTEON specific register definitions to mipsregs.h X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ed918c2daf9ef4c3b52f75736c3a652e5160c8ad;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git MIPS: Add Cavium OCTEON specific register definitions to mipsregs.h Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9316324d070d..207d098f707f 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1000,6 +1000,26 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +/* + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. + */ +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) + +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + /* * Macros to access the floating point coprocessor control registers */