From: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon, 10 Dec 2012 21:26:23 +0000 (+0400)
Subject: xtensa: initialize CPENABLE SR when core has one
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=eab5e7a79d1bb3d607dabf022bfad9f46d1e3ac8;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

xtensa: initialize CPENABLE SR when core has one

XCHAL_CP_NUM is defined in variant/tie.h and it is not included by
head.S, leaving CPENABLE register uninitialised. XCHAL_HAVE_CP is
defined in variant/core.h to 1 when core has CPENABLE SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
---

diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 0cd337a341d9..91d9095284de 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -124,7 +124,7 @@ ENTRY(_startup)
 
 	/* Disable coprocessors. */
 
-#if XCHAL_CP_NUM > 0
+#if XCHAL_HAVE_CP
 	wsr	a0, cpenable
 #endif