From: Dhananjay Phadke Date: Tue, 7 Apr 2009 22:50:48 +0000 (+0000) Subject: netxen: cache align register map table X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ea7eaa39ffadffaa8f1dd1a1f85fa38bf8ae9d39;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git netxen: cache align register map table Aligning register offset translation table imporves performance on rx side. Signed-off-by: Dhananjay Phadke Signed-off-by: David S. Miller --- diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 9439f89869de..3bb2b8c74d92 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c @@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter, } #define CRB_WIN_LOCK_TIMEOUT 100000000 -static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { +static crb_128M_2M_block_map_t +crb_128M_2M_map[64] __cacheline_aligned_in_smp = { {{{0, 0, 0, 0} } }, /* 0: PCI */ {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ {1, 0x0110000, 0x0120000, 0x130000},