From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Thu, 29 May 2014 03:40:13 +0000 (-0500)
Subject: ARM: socfpga: dts: Fix gpio dts entry for the correct clock
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=e9f9fe35f8940c9a4c5deba091d532e3a02bf78b;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

ARM: socfpga: dts: Fix gpio dts entry for the correct clock

The correct clock for the HPS gpio(s) should be the l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7860935ae3a2..b0acaec3b81a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -565,7 +565,7 @@
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff708000 0x1000>;
-			clocks = <&per_base_clk>;
+			clocks = <&l4_mp_clk>;
 			status = "disabled";
 
 			porta: gpio-controller@0 {
@@ -585,7 +585,7 @@
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff709000 0x1000>;
-			clocks = <&per_base_clk>;
+			clocks = <&l4_mp_clk>;
 			status = "disabled";
 
 			portb: gpio-controller@0 {
@@ -605,7 +605,7 @@
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff70a000 0x1000>;
-			clocks = <&per_base_clk>;
+			clocks = <&l4_mp_clk>;
 			status = "disabled";
 
 			portc: gpio-controller@0 {