From: Geert Uytterhoeven Date: Fri, 3 Jun 2016 10:00:09 +0000 (+0200) Subject: serial: sh-sci: Add pin initialization for SCIFA/SCIFB X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=e9d7a45a039913497a57887d85f5decfda4679f0;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git serial: sh-sci: Add pin initialization for SCIFA/SCIFB Before, the driver relied on initialization by the boot loader, or by implicit reset state. Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated RTS/CTS pins are available, which depends on the SoC and UART instance. Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index c46999f20917..b9d027af0f3e 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -712,7 +712,21 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) return; } - if (sci_getreg(port, SCSPTR)->size) { + if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + u16 ctrl = serial_port_in(port, SCPCR); + + /* Enable RXD and TXD pin functions */ + ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); + if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) { + /* RTS# is output, driven 1 */ + ctrl |= SCPCR_RTSC; + serial_port_out(port, SCPDR, + serial_port_in(port, SCPDR) | SCPDR_RTSD); + /* Enable CTS# pin function */ + ctrl &= ~SCPCR_CTSC; + } + serial_port_out(port, SCPCR, ctrl); + } else if (sci_getreg(port, SCSPTR)->size) { u16 status = serial_port_in(port, SCSPTR); /* RTS# is output, driven 1 */