From: Markus Pietrek Date: Tue, 2 Feb 2010 02:29:15 +0000 (+0900) Subject: spi: spi_sh_msiof: Fixed data sampling on the correct edge X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=e8708ef7e86a463b3a5b01d4a9abf16c8748b464;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git spi: spi_sh_msiof: Fixed data sampling on the correct edge The spi_sh_msiof.c driver presently misconfigures REDG and TEDG. TEDG==0 outputs data at the **rising edge** of the clock and REDG==0 samples data at the **falling edge** of the clock. Therefore for SPI, TEDG must be equal to REDG, otherwise the last byte received is not sampled in SPI mode 3. This brings the driver in line with the SH7723 HW Reference Manual settings documented in Figures 20.20 and 20.21 ("SPI Clock and data timing"). Signed-off-by: Markus Pietrek Acked-by: Magnus Damm Signed-off-by: Paul Mundt --- diff --git a/drivers/spi/spi_sh_msiof.c b/drivers/spi/spi_sh_msiof.c index 51e5e1dfa6e5..30973ec16a93 100644 --- a/drivers/spi/spi_sh_msiof.c +++ b/drivers/spi/spi_sh_msiof.c @@ -173,15 +173,12 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, int edge; /* - * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG(!) - * 0 0 10 10 1 0 - * 0 1 10 10 0 1 - * 1 0 11 11 0 1 - * 1 1 11 11 1 0 - * - * (!) Note: REDG is inverted recommended data sheet setting + * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG + * 0 0 10 10 1 1 + * 0 1 10 10 0 0 + * 1 0 11 11 0 0 + * 1 1 11 11 1 1 */ - sh_msiof_write(p, FCTR, 0); sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24)); sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24)); @@ -193,7 +190,7 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, edge = cpol ? cpha : !cpha; tmp |= edge << 27; /* TEDG */ - tmp |= !edge << 26; /* REDG */ + tmp |= edge << 26; /* REDG */ tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ sh_msiof_write(p, CTR, tmp); }