From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Mon, 15 Feb 2016 16:02:13 +0000 (+0200)
Subject: serial: 8250_pci: all known Braswell ports are 1 channel
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=e78240152bd4490c08a22986c9977fe870fc7c98;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

serial: 8250_pci: all known Braswell ports are 1 channel

There is no need to have channel offset defined since all BayTrail and Braswell
ports are 1 channel. Remove unneeded definition.

While here, remove comment which has no value.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 4a8b1078ada7..fb64c74c4256 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -3698,15 +3698,10 @@ static struct pciserial_board pci_boards[] = {
 		.base_baud	= 921600,
 		.reg_shift      = 2,
 	},
-	/*
-	 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
-	 * but is overridden by byt_set_termios.
-	 */
 	[pbn_byt] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 1,
 		.base_baud	= 2764800,
-		.uart_offset	= 0x80,
 		.reg_shift      = 2,
 	},
 	[pbn_qrk] = {