From: Paul Fulghum <paulkf@microgate.com>
Date: Tue, 22 Jul 2008 10:21:39 +0000 (+0100)
Subject: synclink_gt: add serial bit order control
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=e5590717afd5fb6f494323206a1a35ea25610c2d;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git

synclink_gt: add serial bit order control

Add control of hardware serial bit order between LSB first
(default/standard) and MSB first.

Signed-off-by: Paul Fulghum <paulkf@microgate.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---

diff --git a/drivers/char/synclink_gt.c b/drivers/char/synclink_gt.c
index 0e59cf54adaf..3cfc9e1f8882 100644
--- a/drivers/char/synclink_gt.c
+++ b/drivers/char/synclink_gt.c
@@ -4403,6 +4403,8 @@ static void msc_set_vcr(struct slgt_info *info)
 		break;
 	}
 
+	if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
+		val |= BIT4;
 	if (info->signals & SerialSignal_DTR)
 		val |= BIT3;
 	if (info->signals & SerialSignal_RTS)
diff --git a/include/linux/synclink.h b/include/linux/synclink.h
index 45f6bc82d317..c844a229acc9 100644
--- a/include/linux/synclink.h
+++ b/include/linux/synclink.h
@@ -136,6 +136,7 @@
 #define MGSL_INTERFACE_RTS_EN   0x10
 #define MGSL_INTERFACE_LL       0x20
 #define MGSL_INTERFACE_RL       0x40
+#define MGSL_INTERFACE_MSB_FIRST 0x80
 
 typedef struct _MGSL_PARAMS
 {