From: Thierry Reding Date: Tue, 9 Feb 2016 14:52:33 +0000 (+0100) Subject: PCI: tegra: Remove misleading PHYS_OFFSET X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=e32faa303f7f63bad8f9f04267878d61e0f7e0b5;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git PCI: tegra: Remove misleading PHYS_OFFSET BARs are disabled when the size register is 0, so it's misleading to write a base address into the start register. Signed-off-by: Thierry Reding Signed-off-by: Bjorn Helgaas --- diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 7bda73bf7c5e..68d1f41b3cbf 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -771,7 +771,7 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_FPCI_BAR5); /* map all upstream transactions as uncached */ - afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);