From: Rodrigo Vivi Date: Mon, 7 Dec 2015 22:45:20 +0000 (-0800) Subject: drm/i915: Fix idle_frames counter. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=dfaf37baa07513d2c37afff79978807d2d10221a;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: Fix idle_frames counter. 'commit 97173eaf5 ("drm/i915: PSR: Increase idle_frames")' was a mistake. The special case it tried to cover was already being covered by the DP_PSR_NO_TRAIN_ON_EXIT. So this ended up duplicated. So, instead of reverting that let's take this opportunity and unify the idle_frame definition in a single place so we standardize the access and avoid room for that same mistake again. Few changes with this patch: 1. Instead of just respecting the VBT we set a global minumum with max(). So we are sure that we will avoid corner cases in case VBT is doing something we don't understand. 2. Instead of minimum 5 we use 6. When introducing the idle_frames += 4 case we considered that minimum was 2. All because the off-by-one issue. v2: Unified idle_frame definition. Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Paulo Zanoni Link: http://patchwork.freedesktop.org/patch/msgid/1449528320-27655-1-git-send-email-rodrigo.vivi@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index b6609e648f75..1eb1ce5e99c4 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -267,23 +267,17 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t max_sleep_time = 0x1f; - /* Lately it was identified that depending on panel idle frame count - * calculated at HW can be off by 1. So let's use what came - * from VBT + 1. - * There are also other cases where panel demands at least 4 - * but VBT is not being set. To cover these 2 cases lets use - * at least 5 when VBT isn't set to be on the safest side. + /* + * Let's respect VBT in case VBT asks a higher idle_frame value. + * Let's use 6 as the minimum to cover all known cases including + * the off-by-one issue that HW has in some cases. Also there are + * cases where sink should be able to train + * with the 5 or 6 idle patterns. */ - uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ? - dev_priv->vbt.psr.idle_frames + 1 : 5; + uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val = 0x0; const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; - if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { - /* Sink should be able to train with the 5 or 6 idle patterns */ - idle_frames += 4; - } - I915_WRITE(EDP_PSR_CTL, val | (IS_BROADWELL(dev) ? 0 : link_entry_time) | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |