From: Joao Pinto Date: Thu, 10 Mar 2016 20:44:44 +0000 (-0600) Subject: PCI: designware: Add default link up check if sub-driver doesn't override X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=dac29e6c5460d05774e3e8c4fdf4d6e7bd481fab;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git PCI: designware: Add default link up check if sub-driver doesn't override Add a default DesignWare "link_up" test for use when a sub-driver doesn't supply its own pcie_host_ops.link_up() method. [bhelgaas: changelog, split into its own patch] Signed-off-by: Joao Pinto Signed-off-by: Bjorn Helgaas Acked-by: Pratyush Anand --- diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index e4fb44295d61..a4cccd356304 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -70,6 +70,11 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +/* PCIe Port Logic registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 + static struct pci_ops dw_pcie_ops; int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) @@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_port *pp) int dw_pcie_link_up(struct pcie_port *pp) { + u32 val; + if (pp->ops->link_up) return pp->ops->link_up(pp); - return 0; + val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + return val & PCIE_PHY_DEBUG_R1_LINK_UP; } static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,