From: Rex Zhu Date: Tue, 13 Sep 2016 11:38:38 +0000 (+0800) Subject: drm/amdgpu: not set cg for vce/uvd in late init. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d932f37c4aa8b380f8ed529d1472a2ff49b95727;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/amdgpu: not set cg for vce/uvd in late init. no need to set cg for uvd/vce in late init. As when ring test, uvd/vce's dpm will be enabled/disabled. the cg will be set. fix issue suspend when play video or encode, then resume back, the clock will be bypassed on Polaris/Fiji. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d324a079fe9b..3ddae5ff41bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1367,6 +1367,9 @@ static int amdgpu_late_init(struct amdgpu_device *adev) for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_block_status[i].valid) continue; + if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_UVD || + adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_VCE) + continue; /* enable clockgating to save power */ r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, AMD_CG_STATE_GATE);