From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 11 Oct 2007 22:45:58 +0000 (+0100)
Subject: [MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d87d0c930a1591617e4c7c78296b4ba029150188;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git

[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index fe22387d58b1..137183bba54f 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
 	"	addu	%1, %0, 1				\n"
 	"	sc	%1, %2					\n"
 	"	beqz	%1, 1b					\n"
-	"	sync						\n"
+	__WEAK_LLSC_MB
 	: "=&r" (result), "=&r" (temp), "=m" (*pv)
 	: "m" (*pv)
 	: "memory");