From: Linus Torvalds <torvalds@g5.osdl.org>
Date: Wed, 2 Nov 2005 05:49:07 +0000 (-0800)
Subject: Merge master.kernel.org:/pub/scm/linux/kernel/git/airlied/drm-2.6
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d8762748cae4f85b3201c0304969d993b42d5258;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

Merge /pub/scm/linux/kernel/git/airlied/drm-2.6

Manual fixups for some clashes due to re-indenting.
---

d8762748cae4f85b3201c0304969d993b42d5258
diff --cc drivers/char/drm/radeon_cp.c
index 12ef13ff04ca,e64d680899f5..03839ea31092
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@@ -1119,35 -1120,33 +1120,35 @@@ static void radeon_cp_init_ring_buffer(
  	u32 tmp;
  
  	/* Initialize the memory controller */
- 	RADEON_WRITE( RADEON_MC_FB_LOCATION,
- 		      ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
- 		    | ( dev_priv->fb_location >> 16 ) );
+ 	RADEON_WRITE(RADEON_MC_FB_LOCATION,
+ 		     ((dev_priv->gart_vm_start - 1) & 0xffff0000)
+ 		     | (dev_priv->fb_location >> 16));
  
  #if __OS_HAS_AGP
- 	if ( !dev_priv->is_pci ) {
- 		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
- 			      (((dev_priv->gart_vm_start - 1 +
- 				 dev_priv->gart_size) & 0xffff0000) |
- 			       (dev_priv->gart_vm_start >> 16)) );
+ 	if (!dev_priv->is_pci) {
+ 		RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+ 			     (((dev_priv->gart_vm_start - 1 +
+ 				dev_priv->gart_size) & 0xffff0000) |
+ 			      (dev_priv->gart_vm_start >> 16)));
  
  		ring_start = (dev_priv->cp_ring->offset
 -			      - dev->agp->base + dev_priv->gart_vm_start);
 +			      - dev->agp->base
 +			      + dev_priv->gart_vm_start);
  	} else
  #endif
  		ring_start = (dev_priv->cp_ring->offset
 -			      - dev->sg->handle + dev_priv->gart_vm_start);
 +			      - (unsigned long)dev->sg->virtual
 +			      + dev_priv->gart_vm_start);
  
- 	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
+ 	RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
  
  	/* Set the write pointer delay */
- 	RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
+ 	RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
  
  	/* Initialize the ring buffer's read and write pointers */
- 	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
- 	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
- 	SET_RING_HEAD( dev_priv, cur_read_ptr );
+ 	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
+ 	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
+ 	SET_RING_HEAD(dev_priv, cur_read_ptr);
  	dev_priv->ring.tail = cur_read_ptr;
  
  #if __OS_HAS_AGP
@@@ -1164,15 -1162,13 +1164,14 @@@
  		drm_sg_mem_t *entry = dev->sg;
  		unsigned long tmp_ofs, page_ofs;
  
 -		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 +		tmp_ofs = dev_priv->ring_rptr->offset -
 +				(unsigned long)dev->sg->virtual;
  		page_ofs = tmp_ofs >> PAGE_SHIFT;
  
- 		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
- 			     entry->busaddr[page_ofs]);
- 		DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
- 			   (unsigned long) entry->busaddr[page_ofs],
- 			   entry->handle + tmp_ofs );
+ 		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
+ 		DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
+ 			  (unsigned long)entry->busaddr[page_ofs],
+ 			  entry->handle + tmp_ofs);
  	}
  
  	/* Initialize the scratch register pointer.  This will cause
@@@ -1492,24 -1529,21 +1532,21 @@@ static int radeon_do_init_cp(drm_device
  	else
  #endif
  		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
 -						 - dev->sg->handle
 -						 + dev_priv->gart_vm_start);
 +					- (unsigned long)dev->sg->virtual
 +					+ dev_priv->gart_vm_start);
  
- 	DRM_DEBUG( "dev_priv->gart_size %d\n",
- 		   dev_priv->gart_size );
- 	DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
- 		   dev_priv->gart_vm_start );
- 	DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
- 		   dev_priv->gart_buffers_offset );
+ 	DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
+ 	DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
+ 	DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
+ 		  dev_priv->gart_buffers_offset);
  
- 	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
- 	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
+ 	dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
+ 	dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
  			      + init->ring_size / sizeof(u32));
  	dev_priv->ring.size = init->ring_size;
- 	dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
+ 	dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
  
- 	dev_priv->ring.tail_mask =
- 		(dev_priv->ring.size / sizeof(u32)) - 1;
+ 	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
  
  	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;