From: Paulo Zanoni Date: Fri, 12 Jun 2015 17:36:21 +0000 (-0300) Subject: drm/i915: don't set the FBC plane select bits on HSW+ X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d8514d6306ea023f144ac922c4e6e6b283d5b78d;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: don't set the FBC plane select bits on HSW+ This commit is just to make the intentions explicit: on HSW+ these bits are MBZ, but since we only support plane A and the macro evaluates to zero when plane A is the parameter, we're not fixing any bug. v2: - Remove useless extra blank like (Chris). - Init dpfc_ctl in another place (Chris). Signed-off-by: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 1ff288ce84d8..50ed3332def1 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -262,7 +262,10 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) dev_priv->fbc.enabled = true; - dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); + dpfc_ctl = 0; + if (IS_IVYBRIDGE(dev)) + dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane); + if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) dev_priv->fbc.threshold++;