From: Shawn Lin Date: Tue, 16 May 2017 06:30:40 +0000 (+0800) Subject: arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d633becc583e13b38c4aea53b97a197acd61a521;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399 In order to support multiple hierarchy of PCIe buses, for instance, PCIe switch, we need to extent bus-ranges to as max as possible. We have 32 regions and could support up to 31 buses except bus 0 for our root bridge. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 25cb51dd10c5..532b89dd6266 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -220,7 +220,7 @@ #size-cells = <2>; #interrupt-cells = <1>; aspm-no-l0s; - bus-range = <0x0 0x1>; + bus-range = <0x0 0x1f>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; clock-names = "aclk", "aclk-perf",