From: Daniel Cotey <puff65537@bansheeslibrary.com>
Date: Sat, 15 Sep 2012 13:06:20 +0000 (-0700)
Subject: Staging: silicom: bp_mod.h: checkpatch tab and space cleanup
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d5b4f42f8f87ad2f58cea6fd8b3ce419056132ed;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

Staging: silicom: bp_mod.h: checkpatch tab and space cleanup

eleventh chunk of bp_mod.h's cleanup

Signed-off-by: Daniel Cotey <puff65537@bansheeslibrary.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/staging/silicom/bp_mod.h b/drivers/staging/silicom/bp_mod.h
index 2862c5790c28..f59c061660fe 100644
--- a/drivers/staging/silicom/bp_mod.h
+++ b/drivers/staging/silicom/bp_mod.h
@@ -463,28 +463,28 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j)
 	 (pid == SILICOM_PE2G4BPFi35ZX_SSID))
 
 #define BP10G9_IF_SERIES(pid) \
-((pid==INTEL_PE210G2SPI9_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9CX4_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9SR_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9LR_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9T_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9CX4_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9SR_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9LR_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9T_SSID)|| \
-(pid==SILICOM_PE210G2BPI9CX4_SSID)|| \
-(pid==SILICOM_PE210G2BPI9SR_SSID)|| \
-(pid==SILICOM_PE210G2BPI9LR_SSID)|| \
-(pid==SILICOM_PE210G2DBi9SR_SSID)|| \
-(pid==SILICOM_PE210G2DBi9SRRB_SSID)|| \
-(pid==SILICOM_PE210G2DBi9LR_SSID)|| \
-(pid==SILICOM_PE210G2DBi9LRRB_SSID)|| \
-(pid==SILICOM_PE310G4DBi940SR_SSID)|| \
-(pid==SILICOM_PEG2BISC6_SSID)|| \
-(pid==SILICOM_PE310G4BPi9T_SSID)|| \
-(pid==SILICOM_PE310G4BPi9SR_SSID)|| \
-(pid==SILICOM_PE310G4BPi9LR_SSID)|| \
-(pid==SILICOM_PE210G2BPI9T_SSID))
+	((pid == INTEL_PE210G2SPI9_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9CX4_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9SR_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9LR_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9T_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9CX4_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9SR_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9LR_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9T_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9CX4_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9SR_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9LR_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9SR_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9SRRB_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9LR_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9LRRB_SSID) || \
+	 (pid == SILICOM_PE310G4DBi940SR_SSID) || \
+	 (pid == SILICOM_PEG2BISC6_SSID) || \
+	 (pid == SILICOM_PE310G4BPi9T_SSID) || \
+	 (pid == SILICOM_PE310G4BPi9SR_SSID) || \
+	 (pid == SILICOM_PE310G4BPi9LR_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9T_SSID))
 
 /*******************************************************/
 /* 1G INTERFACE ****************************************/