From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Fri, 14 Aug 2015 23:45:51 +0000 (-0700)
Subject: Merge tag 'phy-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux... 
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d50f14805ec0f1cf50654e23559d1dcf81c68b26;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

Merge tag 'phy-for-4.3' of git://git./linux/kernel/git/kishon/linux-phy into usb-next

Kishon writes:

phy: for 4.3

*) Add new NXP USB OTG PHY driver
*) Add vbus/id detection, extcon support and fixes in phy-sun4i-usb
   driver
*) Add support to use phy-sun4i-usb driver for sun8i-a23 and sun8i-a33
   SoCs
*) Other trivial code cleanups, dropping .owner assignment and constify
   phy_ops

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---

d50f14805ec0f1cf50654e23559d1dcf81c68b26
diff --cc drivers/phy/Kconfig
index 6b8dd162f644,0fe9bff7b37b..47da573d0bab
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@@ -54,9 -54,19 +54,20 @@@ config PHY_EXYNOS_MIPI_VIDE
  	  Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
  	  and EXYNOS SoCs.
  
+ config PHY_LPC18XX_USB_OTG
+ 	tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
+ 	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
+ 	depends on MFD_SYSCON
+ 	select GENERIC_PHY
+ 	help
+ 	  Enable this to support NXP LPC18xx/43xx internal USB OTG PHY.
+ 
+ 	  This driver is need for USB0 support on LPC18xx/43xx and takes
+ 	  care of enabling and clock setup.
+ 
  config PHY_PXA_28NM_HSIC
  	tristate "Marvell USB HSIC 28nm PHY Driver"
 +	depends on HAS_IOMEM
  	select GENERIC_PHY
  	help
  	  Enable this to support Marvell USB HSIC PHY driver for Marvell
diff --cc drivers/phy/phy-sun4i-usb.c
index 2dad7e820ff0,623c7143152e..731b395d6e6a
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@@ -212,9 -372,8 +372,9 @@@ void sun4i_usb_phy_set_squelch_detect(s
  
  	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
  }
 +EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
  
- static struct phy_ops sun4i_usb_phy_ops = {
+ static const struct phy_ops sun4i_usb_phy_ops = {
  	.init		= sun4i_usb_phy_init,
  	.exit		= sun4i_usb_phy_exit,
  	.power_on	= sun4i_usb_phy_power_on,
diff --cc drivers/phy/phy-ti-pipe3.c
index 08020dc2c7c8,2038f1945f2c..93bc1120af12
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@@ -256,49 -250,36 +256,49 @@@ static int ti_pipe3_exit(struct phy *x
  	u32 val;
  	unsigned long timeout;
  
 -	/* SATA DPLL can't be powered down due to Errata i783 and PCIe
 -	 * does not have internal DPLL
 +	/* If dpll_reset_syscon is not present we wont power down SATA DPLL
 +	 * due to Errata i783
  	 */
 -	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
 -	    of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
 +	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
 +	    !phy->dpll_reset_syscon)
  		return 0;
  
 -	/* Put DPLL in IDLE mode */
 -	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 -	val |= PLL_IDLE;
 -	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 +	/* PCIe doesn't have internal DPLL */
 +	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 +		/* Put DPLL in IDLE mode */
 +		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 +		val |= PLL_IDLE;
 +		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  
 -	/* wait for LDO and Oscillator to power down */
 -	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 -	do {
 -		cpu_relax();
 -		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 -		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 -			break;
 -	} while (!time_after(jiffies, timeout));
 +		/* wait for LDO and Oscillator to power down */
 +		timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 +		do {
 +			cpu_relax();
 +			val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 +			if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 +				break;
 +		} while (!time_after(jiffies, timeout));
 +
 +		if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 +			dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 +				val);
 +			return -EBUSY;
 +		}
 +	}
  
 -	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 -		dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 -			val);
 -		return -EBUSY;
 +	/* i783: SATA needs control bit toggle after PLL unlock */
 +	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
 +		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 +				   SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
 +		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 +				   SATA_PLL_SOFT_RESET, 0);
  	}
  
 +	ti_pipe3_disable_clocks(phy);
 +
  	return 0;
  }
- static struct phy_ops ops = {
+ static const struct phy_ops ops = {
  	.init		= ti_pipe3_init,
  	.exit		= ti_pipe3_exit,
  	.power_on	= ti_pipe3_power_on,