From: Alan Harrison Date: Thu, 9 Feb 2017 21:01:57 +0000 (-0500) Subject: drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d50e5c24480f8a6e2918ecd998e65f990f88b0ee;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register Add a bit needed during initialization into the driver, where it is supposed to be. Currently, this is happening in the VCE firmware, and although functional, this is the correct place to perform this initialization. Reviewed-by: Leo Liu Signed-off-by: Alan Harrison Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index a8c40eebdd78..a78298529f07 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -510,6 +510,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) WREG32(mmVCE_LMI_SWAP_CNTL, 0); WREG32(mmVCE_LMI_SWAP_CNTL1, 0); WREG32(mmVCE_LMI_VM_CTRL, 0); + WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); + if (adev->asic_type >= CHIP_STONEY) { WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));