From: Peter Hung <hpeter@gmail.com>
Date: Wed, 5 Aug 2015 06:44:53 +0000 (+0800)
Subject: serial: 8250_pci: fix mode after S3/S4 resume for F81504/508/512
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d3159455bf46b71d0a4f2bb5d9cb92b64056e2b1;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

serial: 8250_pci: fix mode after S3/S4 resume for F81504/508/512

Fix RS232/485 mode incorrect setting after S3/S4 resume for F81504/508/512

We had add RS232/485 RTS control with fecf27a373f5. But when it
resume from S3/S4, the mode register 0x40 + 0x08 * idx + 7 will
rewrite to 0x01 (RS232 mode).

This patch will modify 2 sections.

One is pci_fintek_init(), if it called when first init, it will
write mode register with 0x01. If it called from S3/S4 resume,
it's will get the relative port data and pass it to
pci_fintek_rs485_config() with NULL rs485 parameter.

The another modification is in pci_fintek_rs485_config(). It'll
re-apply old configuration when the parameter rs485 is NULL.

Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index e12e91181781..68042dd1c525 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1705,7 +1705,9 @@ static int pci_fintek_rs485_config(struct uart_port *port,
 
 	pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
 
-	if (rs485->flags & SER_RS485_ENABLED)
+	if (!rs485)
+		rs485 = &port->rs485;
+	else if (rs485->flags & SER_RS485_ENABLED)
 		memset(rs485->padding, 0, sizeof(rs485->padding));
 	else
 		memset(rs485, 0, sizeof(*rs485));
@@ -1733,7 +1735,10 @@ static int pci_fintek_rs485_config(struct uart_port *port,
 	}
 
 	pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
-	port->rs485 = *rs485;
+
+	if (rs485 != &port->rs485)
+		port->rs485 = *rs485;
+
 	return 0;
 }
 
@@ -1774,6 +1779,8 @@ static int pci_fintek_init(struct pci_dev *dev)
 	u32 max_port, i;
 	u32 bar_data[3];
 	u8 config_base;
+	struct serial_private *priv = pci_get_drvdata(dev);
+	struct uart_8250_port *port;
 
 	switch (dev->device) {
 	case 0x1104: /* 4 ports */
@@ -1815,8 +1822,18 @@ static int pci_fintek_init(struct pci_dev *dev)
 
 		pci_write_config_byte(dev, config_base + 0x06, dev->irq);
 
-		/* force init to RS232 Mode */
-		pci_write_config_byte(dev, config_base + 0x07, 0x01);
+		if (priv) {
+			/* re-apply RS232/485 mode when
+			 * pciserial_resume_ports()
+			 */
+			port = serial8250_get_port(priv->line[i]);
+			pci_fintek_rs485_config(&port->port, NULL);
+		} else {
+			/* First init without port data
+			 * force init to RS232 Mode
+			 */
+			pci_write_config_byte(dev, config_base + 0x07, 0x01);
+		}
 	}
 
 	return max_port;