From: Roland Dreier Date: Tue, 29 Apr 2014 00:36:20 +0000 (-0700) Subject: cxgb4: Decode PCIe Gen3 link speed X-Git-Tag: MMI-PSA29.97-13-9~12250^2~25 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d2e752db6d05374a35dddb2e17864fe310fbcf69;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git cxgb4: Decode PCIe Gen3 link speed Add handling for " 8 GT/s" in print_port_info(). Signed-off-by: Roland Dreier Signed-off-by: David S. Miller --- diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index 6fe58913403a..24e16e3301e0 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c @@ -5870,6 +5870,8 @@ static void print_port_info(const struct net_device *dev) spd = " 2.5 GT/s"; else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) spd = " 5 GT/s"; + else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) + spd = " 8 GT/s"; if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) bufp += sprintf(bufp, "100/");