From: Andrew Isaacson <adi@broadcom.com>
Date: Thu, 20 Oct 2005 06:54:43 +0000 (-0700)
Subject: Sibyte fixes
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d121ced21d79eab7726bfe6b1e33da4ae86072c0;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git

Sibyte fixes

Fix typo in cpu_probe_sibyte.

Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 72c580d94e24..f7a841573b84 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -612,7 +612,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 	 * cache code which eventually will be folded into c-r4k.c.  Until
 	 * then we pretend it's got it's own cache architecture.
 	 */
-	c->options &= MIPS_CPU_4K_CACHE;
+	c->options &= ~MIPS_CPU_4K_CACHE;
 	c->options |= MIPS_CPU_SB1_CACHE;
 
 	switch (c->processor_id & 0xff00) {