From: Alex Deucher Date: Tue, 27 Jul 2010 15:17:44 +0000 (-0400) Subject: drm/radeon: reorder r6xx/r7xx blit state emit to make more regs sequential X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=d0623a3e74610aff0b984d68bbc027a7e511e686;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/radeon: reorder r6xx/r7xx blit state emit to make more regs sequential Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c index 9a0553c69f1b..9a0c947b342c 100644 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c @@ -96,11 +96,6 @@ const u32 r6xx_default_state[] = 0x00000000, /* DB_STENCIL_CLEAR */ 0x00000000, /* DB_DEPTH_CLEAR */ - 0xc0026900, - 0x0000010c, - 0x00000000, /* DB_STENCILREFMASK */ - 0x00000000, /* DB_STENCILREFMASK_BF */ - 0xc0016900, 0x00000200, 0x00000000, /* DB_DEPTH_CONTROL */ @@ -114,13 +109,19 @@ const u32 r6xx_default_state[] = 0x00000351, 0x0000aa00, /* DB_ALPHA_TO_MASK */ + 0xc0036900, + 0x00000100, + 0x00000800, /* VGT_MAX_VTX_INDX */ + 0x00000000, /* VGT_MIN_VTX_INDX */ + 0x00000000, /* VGT_INDX_OFFSET */ + 0xc0016900, - 0x00000104, - 0x00000000, /* SX_ALPHA_TEST_CONTROL */ + 0x00000103, + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 0xc0016900, - 0x0000010e, - 0x00000000, /* SX_ALPHA_REF */ + 0x00000104, + 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 0xc0076900, 0x00000105, @@ -132,6 +133,15 @@ const u32 r6xx_default_state[] = 0x00000000, 0x00000000, + 0xc0026900, + 0x0000010c, + 0x00000000, /* DB_STENCILREFMASK */ + 0x00000000, /* DB_STENCILREFMASK_BF */ + + 0xc0016900, + 0x0000010e, + 0x00000000, /* SX_ALPHA_REF */ + 0xc0046900, 0x0000030c, 0x01000000, /* CB_CLRCMP_CNTL */ @@ -146,10 +156,6 @@ const u32 r6xx_default_state[] = 0x3f800000, 0x3f800000, - 0xc0016900, - 0x0000008e, - 0x0000000f, /* CB_TARGET_MASK */ - 0xc0016900, 0x00000080, 0x00000000, /* PA_SC_WINDOW_OFFSET */ @@ -234,32 +240,14 @@ const u32 r6xx_default_state[] = 0x00000000, 0x3f800000, - 0xc0016900, - 0x00000293, - 0x00004010, /* PA_SC_MODE_CNTL */ - - 0xc0026900, - 0x00000300, - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - - 0xc0016900, - 0x00000312, - 0xffffffff, /* PA_SC_AA_MASK */ - - 0xc0026900, - 0x00000307, - 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ - 0x00000000, - - 0xc0016900, - 0x00000283, - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0xc0016900, 0x00000292, 0x00000000, /* PA_SC_MPASS_PS_CNTL */ + 0xc0016900, + 0x00000293, + 0x00004010, /* PA_SC_MODE_CNTL */ + 0xc0066900, 0x0000010f, 0x00000000, /* PA_CL_VPORT_0_XSCALE */ @@ -270,9 +258,13 @@ const u32 r6xx_default_state[] = 0x00000000, 0xc0026900, - 0x00000207, - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ + 0x00000300, + 0x00000000, /* PA_SC_LINE_CNTL */ + 0x00000000, /* PA_SC_AA_CONFIG */ + + 0xc0016900, + 0x00000302, + 0x0000002d, /* PA_SU_VTX_CNTL */ 0xc0046900, 0x00000303, @@ -282,45 +274,37 @@ const u32 r6xx_default_state[] = 0x3f800000, 0xc0026900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ + 0x00000307, + 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ + 0x00000000, + + 0xc0016900, + 0x00000312, + 0xffffffff, /* PA_SC_AA_MASK */ 0xc0016900, 0x0000037e, 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 0xc0016900, - 0x00000382, - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ + 0x0000037f, + 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ 0xc0016900, 0x00000380, 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ - 0xc0016900, - 0x00000383, - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ - 0xc0016900, 0x00000381, 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 0xc0016900, - 0x00000282, - 0x00000008, /* PA_SU_LINE_CNTL */ - - 0xc0016900, - 0x00000302, - 0x0000002d, /* PA_SU_VTX_CNTL */ - - 0xc0016900, - 0x0000037f, - 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ + 0x00000382, + 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 0xc0016900, - 0x000001b2, - 0x00000000, /* SPI_THREAD_GROUPING */ + 0x00000383, + 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ 0xc0046900, 0x000001b6, @@ -341,28 +325,27 @@ const u32 r6xx_default_state[] = 0x00000237, 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ - 0xc0036900, - 0x00000100, - 0x00000800, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0xc0026900, 0x000002a8, 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ + 0xc0026900, + 0x00000280, + 0x00000000, /* PA_SU_POINT_SIZE */ + 0x00000000, /* PA_SU_POINT_MINMAX */ + 0xc0016900, - 0x00000103, - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + 0x00000282, + 0x00000008, /* PA_SU_LINE_CNTL */ 0xc0016900, - 0x00000284, - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ + 0x00000283, + 0x00000000, /* PA_SC_LINE_STIPPLE */ 0xc0016900, - 0x00000290, - 0x00000000, /* VGT_GS_MODE */ + 0x00000284, + 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 0xc0016900, 0x00000285, @@ -381,6 +364,10 @@ const u32 r6xx_default_state[] = 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ + 0xc0016900, + 0x00000290, + 0x00000000, /* VGT_GS_MODE */ + 0xc0016900, 0x000002a1, 0x00000000, /* VGT_PRIMITIVEID_EN */ @@ -400,18 +387,33 @@ const u32 r6xx_default_state[] = 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 0xc0016900, - 0x00000206, - 0x00000100, /* PA_CL_VTE_CNTL */ + 0x00000202, + 0x00cc0000, /* CB_COLOR_CONTROL */ + + 0xc0016900, + 0x00000203, + 0x00000210, /* DB_SHADER_CNTL */ 0xc0016900, 0x00000204, 0x00010000, /* PA_CL_CLIP_CNTL */ - 0xc0036e00, /* SET_SAMPLER */ - 0x00000000, - 0x00000012, - 0x00000000, - 0x00000000, + 0xc0016900, + 0x00000205, + 0x00000244, /* PA_SU_SC_MODE_CNTL */ + + 0xc0016900, + 0x00000206, + 0x00000100, /* PA_CL_VTE_CNTL */ + + 0xc0026900, + 0x00000207, + 0x00000000, /* PA_CL_VS_OUT_CNTL */ + 0x00000000, /* PA_CL_NANINF_CNTL */ + + 0xc0016900, + 0x0000008e, + 0x0000000f, /* CB_TARGET_MASK */ 0xc0016900, 0x0000008f, @@ -422,37 +424,35 @@ const u32 r6xx_default_state[] = 0x00000001, /* CB_SHADER_CONTROL */ 0xc0016900, - 0x00000202, - 0x00cc0000, /* CB_COLOR_CONTROL */ - - 0xc0016900, - 0x00000205, - 0x00000244, /* PA_SU_SC_MODE_CNTL */ + 0x00000185, + 0x00000000, /* SPI_VS_OUT_ID_0 */ 0xc0016900, - 0x00000203, - 0x00000210, /* DB_SHADER_CNTL */ + 0x00000191, + 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ 0xc0016900, 0x000001b1, 0x00000000, /* SPI_VS_OUT_CONFIG */ 0xc0016900, - 0x00000185, - 0x00000000, /* SPI_VS_OUT_ID_0 */ + 0x000001b2, + 0x00000000, /* SPI_THREAD_GROUPING */ 0xc0026900, 0x000001b3, 0x00000001, /* SPI_PS_IN_CONTROL_0 */ 0x00000000, /* SPI_PS_IN_CONTROL_1 */ - 0xc0016900, - 0x00000191, - 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ - 0xc0016900, 0x000001b5, 0x00000000, /* SPI_INTERP_CONTROL_0 */ + + 0xc0036e00, /* SET_SAMPLER */ + 0x00000000, + 0x00000012, + 0x00000000, + 0x00000000, }; const u32 r7xx_default_state[] = @@ -511,11 +511,6 @@ const u32 r7xx_default_state[] = 0x00000000, /* DB_STENCIL_CLEAR */ 0x00000000, /* DB_DEPTH_CLEAR */ - 0xc0026900, - 0x0000010c, - 0x00000000, /* DB_STENCILREFMASK */ - 0x00000000, /* DB_STENCILREFMASK_BF */ - 0xc0016900, 0x00000200, 0x00000000, /* DB_DEPTH_CONTROL */ @@ -529,13 +524,19 @@ const u32 r7xx_default_state[] = 0x00000351, 0x0000aa00, /* DB_ALPHA_TO_MASK */ + 0xc0036900, + 0x00000100, + 0x00000800, /* VGT_MAX_VTX_INDX */ + 0x00000000, /* VGT_MIN_VTX_INDX */ + 0x00000000, /* VGT_INDX_OFFSET */ + 0xc0016900, - 0x00000104, - 0x00000000, /* SX_ALPHA_TEST_CONTROL */ + 0x00000103, + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 0xc0016900, - 0x0000010e, - 0x00000000, /* SX_ALPHA_REF */ + 0x00000104, + 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 0xc0046900, 0x00000105, @@ -544,6 +545,15 @@ const u32 r7xx_default_state[] = 0x00000000, 0x00000000, + 0xc0026900, + 0x0000010c, + 0x00000000, /* DB_STENCILREFMASK */ + 0x00000000, /* DB_STENCILREFMASK_BF */ + + 0xc0016900, + 0x0000010e, + 0x00000000, /* SX_ALPHA_REF */ + 0xc0046900, 0x0000030c, /* CB_CLRCMP_CNTL */ 0x01000000, @@ -551,10 +561,6 @@ const u32 r7xx_default_state[] = 0x00000000, 0x00000000, - 0xc0016900, - 0x0000008e, - 0x0000000f, /* CB_TARGET_MASK */ - 0xc0016900, 0x00000080, 0x00000000, /* PA_SC_WINDOW_OFFSET */ @@ -639,32 +645,14 @@ const u32 r7xx_default_state[] = 0x00000000, 0x3f800000, - 0xc0016900, - 0x00000293, - 0x00514000, /* PA_SC_MODE_CNTL */ - - 0xc0026900, - 0x00000300, - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - - 0xc0016900, - 0x00000312, - 0xffffffff, /* PA_SC_AA_MASK */ - - 0xc0026900, - 0x00000307, - 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ - 0x00000000, - - 0xc0016900, - 0x00000283, - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0xc0016900, 0x00000292, 0x00000000, /* PA_SC_MPASS_PS_CNTL */ + 0xc0016900, + 0x00000293, + 0x00514000, /* PA_SC_MODE_CNTL */ + 0xc0066900, 0x0000010f, 0x00000000, /* PA_CL_VPORT_0_XSCALE */ @@ -675,9 +663,13 @@ const u32 r7xx_default_state[] = 0x00000000, 0xc0026900, - 0x00000207, - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ + 0x00000300, + 0x00000000, /* PA_SC_LINE_CNTL */ + 0x00000000, /* PA_SC_AA_CONFIG */ + + 0xc0016900, + 0x00000302, + 0x0000002d, /* PA_SU_VTX_CNTL */ 0xc0046900, 0x00000303, @@ -687,45 +679,37 @@ const u32 r7xx_default_state[] = 0x3f800000, 0xc0026900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ + 0x00000307, + 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ + 0x00000000, + + 0xc0016900, + 0x00000312, + 0xffffffff, /* PA_SC_AA_MASK */ 0xc0016900, 0x0000037e, 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 0xc0016900, - 0x00000382, - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ + 0x0000037f, + 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ 0xc0016900, 0x00000380, 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ - 0xc0016900, - 0x00000383, - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ - 0xc0016900, 0x00000381, 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 0xc0016900, - 0x00000282, - 0x00000008, /* PA_SU_LINE_CNTL */ - - 0xc0016900, - 0x00000302, - 0x0000002d, /* PA_SU_VTX_CNTL */ - - 0xc0016900, - 0x0000037f, - 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ + 0x00000382, + 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 0xc0016900, - 0x000001b2, - 0x00000001, /* SPI_THREAD_GROUPING */ + 0x00000383, + 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ 0xc0046900, 0x000001b6, @@ -746,28 +730,27 @@ const u32 r7xx_default_state[] = 0x00000237, 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ - 0xc0036900, - 0x00000100, - 0x00000800, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0xc0026900, 0x000002a8, 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ + 0xc0026900, + 0x00000280, + 0x00000000, /* PA_SU_POINT_SIZE */ + 0x00000000, /* PA_SU_POINT_MINMAX */ + 0xc0016900, - 0x00000103, - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + 0x00000282, + 0x00000008, /* PA_SU_LINE_CNTL */ 0xc0016900, - 0x00000284, - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ + 0x00000283, + 0x00000000, /* PA_SC_LINE_STIPPLE */ 0xc0016900, - 0x00000290, - 0x00000000, /* VGT_GS_MODE */ + 0x00000284, + 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 0xc00b6900, 0x00000285, @@ -783,6 +766,10 @@ const u32 r7xx_default_state[] = 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ + 0xc0016900, + 0x00000290, + 0x00000000, /* VGT_GS_MODE */ + 0xc0016900, 0x000002a1, 0x00000000, /* VGT_PRIMITIVEID_EN */ @@ -802,18 +789,33 @@ const u32 r7xx_default_state[] = 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 0xc0016900, - 0x00000206, - 0x00000100, /* PA_CL_VTE_CNTL */ + 0x00000202, + 0x00cc0000, /* CB_COLOR_CONTROL */ + + 0xc0016900, + 0x00000203, + 0x00000210, /* DB_SHADER_CNTL */ 0xc0016900, 0x00000204, 0x00010000, /* PA_CL_CLIP_CNTL */ - 0xc0036e00, /* SET_SAMPLER */ - 0x00000000, - 0x00000012, - 0x00000000, - 0x00000000, + 0xc0016900, + 0x00000205, + 0x00000244, /* PA_SU_SC_MODE_CNTL */ + + 0xc0016900, + 0x00000206, + 0x00000100, /* PA_CL_VTE_CNTL */ + + 0xc0026900, + 0x00000207, + 0x00000000, /* PA_CL_VS_OUT_CNTL */ + 0x00000000, /* PA_CL_NANINF_CNTL */ + + 0xc0016900, + 0x0000008e, + 0x0000000f, /* CB_TARGET_MASK */ 0xc0016900, 0x0000008f, @@ -824,37 +826,35 @@ const u32 r7xx_default_state[] = 0x00000001, /* CB_SHADER_CONTROL */ 0xc0016900, - 0x00000202, - 0x00cc0000, /* CB_COLOR_CONTROL */ - - 0xc0016900, - 0x00000205, - 0x00000244, /* PA_SU_SC_MODE_CNTL */ + 0x00000185, + 0x00000000, /* SPI_VS_OUT_ID_0 */ 0xc0016900, - 0x00000203, - 0x00000210, /* DB_SHADER_CNTL */ + 0x00000191, + 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ 0xc0016900, 0x000001b1, 0x00000000, /* SPI_VS_OUT_CONFIG */ 0xc0016900, - 0x00000185, - 0x00000000, /* SPI_VS_OUT_ID_0 */ + 0x000001b2, + 0x00000001, /* SPI_THREAD_GROUPING */ 0xc0026900, 0x000001b3, 0x00000001, /* SPI_PS_IN_CONTROL_0 */ 0x00000000, /* SPI_PS_IN_CONTROL_1 */ - 0xc0016900, - 0x00000191, - 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ - 0xc0016900, 0x000001b5, 0x00000000, /* SPI_INTERP_CONTROL_0 */ + + 0xc0036e00, /* SET_SAMPLER */ + 0x00000000, + 0x00000012, + 0x00000000, + 0x00000000, }; /* same for r6xx/r7xx */