From: Hendrik Brueckner Date: Mon, 7 Dec 2009 11:44:42 +0000 (+0100) Subject: [S390] s390: clear high-order bits of registers after sam64 X-Git-Tag: MMI-PSA29.97-13-9~25715^2~71 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=cf87b7439ec81b9374e7772e44e9cb2eb9e57160;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git [S390] s390: clear high-order bits of registers after sam64 When the kernel is IPLed without the CLEAR option and switches to 64-bit, the high-order half of the registers might contain random values. This can cause addressing exceptions and the kernel enters an interrupt loop. Initialize the high-order half of the general purpose registers with zeros after switching to 64-bit mode. Cc: Signed-off-by: Hendrik Brueckner Signed-off-by: Martin Schwidefsky --- diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S index 6a250808092b..d984a2a380c3 100644 --- a/arch/s390/kernel/head64.S +++ b/arch/s390/kernel/head64.S @@ -83,6 +83,8 @@ startup_continue: slr %r0,%r0 # set cpuid to zero sigp %r1,%r0,0x12 # switch to esame mode sam64 # switch to 64 bit mode + llgfr %r13,%r13 # clear high-order half of base reg + lmh %r0,%r15,.Lzero64-.LPG1(%r13) # clear high-order half lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area # move IPL device to lowcore @@ -127,6 +129,7 @@ startup_continue: .L4malign:.quad 0xffffffffffc00000 .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 .Lnop: .long 0x07000700 +.Lzero64:.fill 16,4,0x0 #ifdef CONFIG_ZFCPDUMP .Lcurrent_cpu: .long 0x0