From: Chander Kashyap Date: Thu, 26 Sep 2013 09:06:35 +0000 (+0530) Subject: clk: exynos5420: fix cpll clock register offsets X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=cdf64eeeb0d762585e2126f3024458d199c2635d;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git clk: exynos5420: fix cpll clock register offsets Fixes cpll control and lock register offset values for Exynos5420 SoC. Signed-off-by: Chander Kashyap Acked-by: Kukjin Kim Signed-off-by: Mike Turquette --- diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 48c4a9350b91..87ea79633862 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -737,8 +737,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), - [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, - MPLL_CON0, NULL), + [cpll] = PLL(pll_2550, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK, + CPLL_CON0, NULL), [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, DPLL_CON0, NULL), [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,