From: Maciej W. Rozycki Date: Fri, 3 Apr 2015 22:26:32 +0000 (+0100) Subject: MIPS: Fix BREAK code interpretation heuristics X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c9875032015ec94033295382a098657d4e38bf89;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git MIPS: Fix BREAK code interpretation heuristics Do not lose the other half of the BREAK code where there is an upper half. This is so that e.g. `BREAK 7, 7' is not interpreted as a divide by zero trap, while `BREAK 0, 7' or `BREAK 7, 0' still are. Signed-off-by: Maciej W. Rozycki Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9697/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a671d3358eb6..dc6eaf4d93ea 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -943,7 +943,7 @@ asmlinkage void do_bp(struct pt_regs *regs) * We handle both cases with a simple heuristics. --macro */ if (bcode >= (1 << 10)) - bcode >>= 10; + bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); /* * notify the kprobe handlers, if instruction is likely to