From: Dave Airlie Date: Thu, 18 Jun 2015 02:53:54 +0000 (+1000) Subject: Merge tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux into... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c861acc4d5fc249a0febf38dfebbb431b21628dd;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Merge tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.2-rc1 This contains a couple of mostly fixes for issues that have crept up in recent versions of linux-next. One issue is that DP AUX transactions of more than 4 bytes will access the wrong FIFO registers and hence become corrupt. Another fix is required to restore functionality of Tegra20 if using the GART. The current code expects the IOMMU aperture to be the complete 4 GiB address space, whereas the GART on Tegra20 only provides a 128 MiB aperture. One more issue with IOMMU support is that on 64-bit ARM, swiotlb is the default IOMMU implementation backing the DMA API. A side-effect of that is that when dma_map_sg() is called to flush caches (yes, this is a bit of a hack, but ARM does not provide a better API), swiotlb will immediately run out of memory because its bounce buffer is too small to make a framebuffer. Finally I've included a mostly cosmetic fix that stores register values in u32 rather than unsigned long to avoid sign-extension issues on 64- bit ARM. This is only a precaution since it hasn't caused any issues (yet). * tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: dpaux: Registers are 32-bit drm/tegra: gem: Flush pages after allocation drm/tegra: gem: Take into account IOMMU aperture drm/tegra: dpaux: Fix transfers larger than 4 bytes --- c861acc4d5fc249a0febf38dfebbb431b21628dd