From: Chris Wilson Date: Wed, 24 Aug 2016 18:00:53 +0000 (+0100) Subject: Revert "drm/i915/fbc: Allow on unfenced surfaces, for recent gen" X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c82dd8848479d27dec3f05e9a0980a83fcadca8b;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Revert "drm/i915/fbc: Allow on unfenced surfaces, for recent gen" This reverts commit 8678fdaf396c ("drm/i915/fbc: Allow on unfenced surfaces, for recent gen") as Skylake has issues with unfenced FBC tracking (and yes Skylake doesn't even enable FBC yet). Paulo would like to do a full review of all existing workarounds to see if any more are missing prior to allowing FBC on unfenced surfaces. In the meantime lets hope that all framebuffers are idle and naturally fit within the mappable aperture. Requested-by: Paulo Zanoni Fixes: 8678fdaf396c ("drm/i915/fbc: Allow on unfenced surfaces..."); Cc: Paulo Zanoni Link: http://patchwork.freedesktop.org/patch/msgid/20160824180053.24239-1-chris@chris-wilson.co.uk Signed-off-by: Chris Wilson --- diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index bf8b22ad9aed..faa67624e1ed 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -799,10 +799,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) */ if (cache->fb.tiling_mode != I915_TILING_X || cache->fb.fence_reg == I915_FENCE_REG_NONE) { - if (INTEL_GEN(dev_priv) < 5) { - fbc->no_fbc_reason = "framebuffer not tiled or fenced"; - return false; - } + fbc->no_fbc_reason = "framebuffer not tiled or fenced"; + return false; } if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && cache->plane.rotation != DRM_ROTATE_0) {