From: Alexandre Courbot <acourbot@nvidia.com>
Date: Wed, 29 Mar 2017 09:31:13 +0000 (+0900)
Subject: drm/nouveau/secboot/gm20b: specify MC base address as argument
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c79505c1f9e14d7aa9eb3b085c799d77950b1e20;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

drm/nouveau/secboot/gm20b: specify MC base address as argument

Allow the MC base address to be specified as an argument for the WPR
region reading function. GP10B uses a different address layout as GM20B,
so this is necessary. Also export the function to be used by GP10B.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
index 6dc9fc384f24..c8ab3d76bdef 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
@@ -41,4 +41,7 @@ void *gm200_secboot_dtor(struct nvkm_secboot *);
 int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *,
 			   struct nvkm_falcon *);
 
+/* Tegra-only */
+int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32);
+
 #endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
index 29e6f73dfd7e..b10ed59a4911 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
@@ -23,28 +23,29 @@
 #include "acr.h"
 #include "gm200.h"
 
+#define TEGRA210_MC_BASE			0x70019000
+
 #ifdef CONFIG_ARCH_TEGRA
-#define TEGRA_MC_BASE				0x70019000
 #define MC_SECURITY_CARVEOUT2_CFG0		0xc58
 #define MC_SECURITY_CARVEOUT2_BOM_0		0xc5c
 #define MC_SECURITY_CARVEOUT2_BOM_HI_0		0xc60
 #define MC_SECURITY_CARVEOUT2_SIZE_128K		0xc64
 #define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED	(1 << 1)
 /**
- * sb_tegra_read_wpr() - read the WPR registers on Tegra
+ * gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra
  *
  * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region
  * is reserved from system memory by the bootloader and irreversibly locked.
  * This function reads the address and size of the pre-configured WPR region.
  */
-static int
-gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
+int
+gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
 {
 	struct nvkm_secboot *sb = &gsb->base;
 	void __iomem *mc;
 	u32 cfg;
 
-	mc = ioremap(TEGRA_MC_BASE, 0xd00);
+	mc = ioremap(mc_base, 0xd00);
 	if (!mc) {
 		nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
 		return PTR_ERR(mc);
@@ -70,8 +71,8 @@ gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
 	return 0;
 }
 #else
-static int
-gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
+int
+gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
 {
 	nvkm_error(&gsb->base.subdev, "Tegra support not compiled in\n");
 	return -EINVAL;
@@ -84,7 +85,7 @@ gm20b_secboot_oneinit(struct nvkm_secboot *sb)
 	struct gm200_secboot *gsb = gm200_secboot(sb);
 	int ret;
 
-	ret = gm20b_tegra_read_wpr(gsb);
+	ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA210_MC_BASE);
 	if (ret)
 		return ret;