From: Linus Torvalds Date: Wed, 12 Jul 2006 15:29:46 +0000 (-0700) Subject: Add PIIX4 APCI quirk for the 440MX chipset too X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c67646641cab01c93a56674bfcd963f55442dad5;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git Add PIIX4 APCI quirk for the 440MX chipset too This is confirmed to fix a hang due to PCI resource conflicts with setting up the Cardbus bridge on old laptops with the 440MX chipsets. Original report by Alessio Sangalli, lspci debugging help by Pekka Enberg, and trial patch suggested by Daniel Ritz: "From the docs available i would _guess_ this thing is really similar to the 82443BX/82371AB combination. at least the SMBus base address register is hidden at the very same place (32bit at 0x90 in function 3 of the "south" brigde)" The dang thing is largely undocumented, but the patch was corroborated by Asit Mallick: "I am trying to find the register information. 440MX is an integration of 440BX north-bridge without AGP and PIIX4E (82371EB). PIIX4 quirk should cover the ACPI and SMBus related I/O registers." and verified to fix the problem by Alessio. Cc: Daniel Ritz Cc: Asit Mallick Cc: Pekka Enberg Cc: Ivan Kokshaysky Cc: Dmitry Torokhov Tested-by: Alessio Sangalli Signed-off-by: Linus Torvalds --- diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d1d7333bb71b..e9a57afa1a08 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -400,6 +400,7 @@ static void __devinit quirk_piix4_acpi(struct pci_dev *dev) piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); /* * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at