From: Ville Syrjälä Date: Wed, 5 Feb 2014 10:43:47 +0000 (+0200) Subject: drm/i915: Add a comment about WIZ hashing vs. thread counts X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c5c98a58990c1b2cf4d94b6759bed239976e5305;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: Add a comment about WIZ hashing vs. thread counts Add a comment next to our WIZ hashing setup to remind people about the link between WIZ hashing disable bit and PS/WM thread counts. Suggested-by: Chris Wilson Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 151afe53cc7c..3e754fec58b5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4664,6 +4664,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) /* * BSpec recoomends 8x4 when MSAA is used, * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ I915_WRITE(GEN6_GT_MODE, GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); @@ -4847,6 +4851,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) /* * BSpec recommends 8x4 when MSAA is used, * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ I915_WRITE(GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); @@ -4883,6 +4891,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* * BSpec recommends 8x4 when MSAA is used, * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ I915_WRITE(GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); @@ -4971,6 +4983,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) /* * BSpec recommends 8x4 when MSAA is used, * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ I915_WRITE(GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);