From: H Hartley Sweeten Date: Fri, 20 Jun 2014 20:13:01 +0000 (-0700) Subject: staging: comedi: dt282x: fix bug where DIO direction is reset to inputs X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c50d32de3707ee8165eaeaa319c5c13d12ea0669;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git staging: comedi: dt282x: fix bug where DIO direction is reset to inputs The direction of the 16 DIO channels is controlled with two bits in the DACSR register. The HBOE bit controls the direction of channels 15-8 and the LBOE bit channels 7-0. The DACSR register is also used to control the Analog Output async command support. Currently, starting or canceling an Analog Output command would also reset the DIO directions so that all channels were inputs. Fix the driver so that the DIO direction is not changed when starting or canceling an Analog Output async command. Signed-off-by: H Hartley Sweeten Reviewed-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/comedi/drivers/dt282x.c b/drivers/staging/comedi/drivers/dt282x.c index 6e813bb562e8..e30a0646f4f1 100644 --- a/drivers/staging/comedi/drivers/dt282x.c +++ b/drivers/staging/comedi/drivers/dt282x.c @@ -993,9 +993,12 @@ static int dt282x_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) outw(devpriv->divisor, dev->iobase + DT2821_TMRCTR_REG); - devpriv->dacsr = DT2821_DACSR_SSEL | - DT2821_DACSR_DACLK | - DT2821_DACSR_IDARDY; + /* clear all bits but the DIO direction bits */ + devpriv->dacsr &= (DT2821_DACSR_LBOE | DT2821_DACSR_HBOE); + + devpriv->dacsr |= (DT2821_DACSR_SSEL | + DT2821_DACSR_DACLK | + DT2821_DACSR_IDARDY); outw(devpriv->dacsr, dev->iobase + DT2821_DACSR_REG); s->async->inttrig = dt282x_ao_inttrig; @@ -1010,7 +1013,9 @@ static int dt282x_ao_cancel(struct comedi_device *dev, dt282x_disable_dma(dev); - devpriv->dacsr = 0; + /* clear all bits but the DIO direction bits */ + devpriv->dacsr &= (DT2821_DACSR_LBOE | DT2821_DACSR_HBOE); + outw(devpriv->dacsr, dev->iobase + DT2821_DACSR_REG); devpriv->supcsr = 0;