From: Thierry Reding Date: Thu, 26 Mar 2015 16:53:01 +0000 (+0100) Subject: clk: tegra: Use the proper parent for plld_dsi X-Git-Tag: MMI-PSA29.97-13-9~10216^2~5^2 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c1d676cec572544616273d5853cb7cc38fbaa62b;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git clk: tegra: Use the proper parent for plld_dsi The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index f1fa29ec7951..11f857cd5f6a 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1113,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; - clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0, + clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC, 30, 0, &pll_d_lock); - clks[TEGRA124_CLK_PLLD_DSI] = clk; + clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; - clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base, - 0, 48, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, + clk_base, 0, 48, + periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIA] = clk; - clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base, - 0, 82, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, + clk_base, 0, 82, + periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIB] = clk; /* emc mux */ diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index ae2eb17a1658..a2156090563f 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -297,7 +297,7 @@ #define TEGRA124_CLK_PLL_C4 270 #define TEGRA124_CLK_PLL_DP 271 #define TEGRA124_CLK_PLL_E_MUX 272 -#define TEGRA124_CLK_PLLD_DSI 273 +#define TEGRA124_CLK_PLL_D_DSI_OUT 273 /* 274 */ /* 275 */ /* 276 */