From: Rodrigo Vivi Date: Thu, 10 Aug 2017 22:45:25 +0000 (-0700) Subject: drm/i915/cnl: Dump the right pll registers when dumping pipe config. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=c1b56c52aa3c38982b801a36f9b7de96077579f4;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915/cnl: Dump the right pll registers when dumping pipe config. Different from SKL we don't need ctrl1 and cfgcr2, but we need to dump cfgcr0 and cfgcr1 instead. v2: rebase and commit message Cc: Clint Taylor Cc: Mika Kahola Signed-off-by: Rodrigo Vivi Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20170810224525.18278-1-rodrigo.vivi@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 2f7b0e64f628..a2a3d93d67bd 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2379,6 +2379,15 @@ cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, return pll; } +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, + struct intel_dpll_hw_state *hw_state) +{ + DRM_DEBUG_KMS("dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); +} + static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { .enable = cnl_ddi_pll_enable, .disable = cnl_ddi_pll_disable, @@ -2395,7 +2404,7 @@ static const struct dpll_info cnl_plls[] = { static const struct intel_dpll_mgr cnl_pll_mgr = { .dpll_info = cnl_plls, .get_dpll = cnl_get_dpll, - .dump_hw_state = skl_dump_hw_state, + .dump_hw_state = cnl_dump_hw_state, }; /**