From: Ben Skeggs <bskeggs@redhat.com>
Date: Wed, 21 Nov 2012 04:49:54 +0000 (+1000)
Subject: drm/nouveau/disp: add support for 10bpc over DisplayPort
X-Git-Tag: MMI-PSA29.97-13-9~15304^2~48
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bf2c886a857dcf61f2354796a8858a230f2737fa;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git

drm/nouveau/disp: add support for 10bpc over DisplayPort

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index c9cfd02f94ab..c6f80055e988 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -973,7 +973,6 @@ nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
 	const u32 soff = (  or * 0x800);
 	const u32 loff = (link * 0x080) + soff;
 	const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
-	const u32 bits = ((ctrl & 0x000f0000) == 0x00020000) ? 18 : 24;
 	const u32 symbol = 100000;
 	u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
 	u32 clksor = nv_rd32(priv, 0x614300 + soff);
@@ -981,7 +980,7 @@ nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
 	int TU, VTUi, VTUf, VTUa;
 	u64 link_data_rate, link_ratio, unk;
 	u32 best_diff = 64 * symbol;
-	u32 link_nr, link_bw, r;
+	u32 link_nr, link_bw, bits, r;
 
 	/* calculate packed data rate for each lane */
 	if      (dpctrl > 0x00030000) link_nr = 4;
@@ -993,6 +992,10 @@ nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
 	else
 		link_bw = 162000;
 
+	if      ((ctrl & 0xf0000) == 0x60000) bits = 30;
+	else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
+	else                                  bits = 18;
+
 	link_data_rate = (pclk * bits / 8) / link_nr;
 
 	/* calculate ratio of packed data rate to link symbol rate */
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 24bcbc6a88bb..9e38ebff5fb3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -711,7 +711,6 @@ nvd0_display_unk2_calc_tu(struct nv50_disp_priv *priv, int head, int or)
 	const u32 ctrl = nv_rd32(priv, 0x660200 + (or   * 0x020));
 	const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300));
 	const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
-	const u32 bits = ((conf & 0x3c0) == 0x080) ? 18 : 24;
 	const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
 	const u32 hoff = (head * 0x800);
 	const u32 soff = (  or * 0x800);
@@ -720,10 +719,14 @@ nvd0_display_unk2_calc_tu(struct nv50_disp_priv *priv, int head, int or)
 	const u32 TU = 64;
 	u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x000f0000;
 	u32 clksor = nv_rd32(priv, 0x612300 + soff);
-	u32 datarate = (pclk * bits) / 8;
-	u32 link_nr, link_bw;
+	u32 datarate, link_nr, link_bw, bits;
 	u64 ratio, value;
 
+	if      ((conf & 0x3c0) == 0x180) bits = 30;
+	else if ((conf & 0x3c0) == 0x140) bits = 24;
+	else                              bits = 18;
+	datarate = (pclk * bits) / 8;
+
 	if      (dpctrl > 0x00030000) link_nr = 4;
 	else if (dpctrl > 0x00010000) link_nr = 2;
 	else			      link_nr = 1;
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 7c77b282d816..b252dbe0f4e0 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1791,9 +1791,13 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
 		if (nv_connector->base.display_info.bpc == 6) {
 			nv_encoder->dp.datarate = mode->clock * 18 / 8;
 			depth = 0x2;
-		} else {
+		} else
+		if (nv_connector->base.display_info.bpc == 8) {
 			nv_encoder->dp.datarate = mode->clock * 24 / 8;
 			depth = 0x5;
+		} else {
+			nv_encoder->dp.datarate = mode->clock * 30 / 8;
+			depth = 0x6;
 		}
 
 		if (nv_encoder->dcb->sorconf.link & 1)