From: Dirk Behme Date: Fri, 19 Feb 2016 06:50:12 +0000 (+0100) Subject: ARM: imx: Do L2 errata only if the L2 cache isn't enabled X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bc3d8ede3a1d1336507d6a382764319cbbc9cf7a;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git ARM: imx: Do L2 errata only if the L2 cache isn't enabled All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped. The write to the L2-Cache controller from non-secure world causes an imprecise external abort. This is needed in scenarios where one of the cores runs an other OS, e.g. an RTOS. For the i.MX6 specific L2 cache handling we missed this check. Add it. Signed-off-by: Marcel Grosshans Signed-off-by: Dirk Behme Signed-off-by: Shawn Guo --- diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 93d4a9a39353..105d1ce4ed9d 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -106,6 +106,9 @@ void __init imx_init_l2cache(void) goto out; } + if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) + goto skip_if_enabled; + /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= 0x70800000; @@ -122,6 +125,7 @@ void __init imx_init_l2cache(void) val &= ~(1 << 30 | 1 << 23); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); +skip_if_enabled: iounmap(l2x0_base); of_node_put(np);