From: Alexey Kardashevskiy Date: Fri, 6 Jun 2014 08:44:02 +0000 (+1000) Subject: powerpc/powernv: Use it_page_shift in TCE build X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bc32057ed5cdb9ca1fe98af1363e26c0a4d14b5f;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git powerpc/powernv: Use it_page_shift in TCE build This makes use of iommu_table::it_page_shift instead of TCE_SHIFT and TCE_RPN_SHIFT hardcoded values. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Benjamin Herrenschmidt --- diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c index f91a4e5d872e..b6cb9966f100 100644 --- a/arch/powerpc/platforms/powernv/pci.c +++ b/arch/powerpc/platforms/powernv/pci.c @@ -564,10 +564,11 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, proto_tce |= TCE_PCI_WRITE; tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; - rpn = __pa(uaddr) >> TCE_SHIFT; + rpn = __pa(uaddr) >> tbl->it_page_shift; while (npages--) - *(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT)); + *(tcep++) = cpu_to_be64(proto_tce | + (rpn++ << tbl->it_page_shift)); /* Some implementations won't cache invalid TCEs and thus may not * need that flush. We'll probably turn it_type into a bit mask