From: Kevin Cernekee Date: Tue, 21 Oct 2014 04:27:58 +0000 (-0700) Subject: MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bbf2ba67cdbdb3676a661c3eba5572d1e513627f;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2 line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be cacheline-aligned and terrible things will happen. Signed-off-by: Kevin Cernekee Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8164/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 992f98361e5a..002cf4c56ebf 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1587,12 +1587,14 @@ config CPU_BMIPS4350 config CPU_BMIPS4380 bool + select MIPS_L1_CACHE_SHIFT_6 select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU config CPU_BMIPS5000 bool select MIPS_CPU_SCACHE + select MIPS_L1_CACHE_SHIFT_7 select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU