From: Jianqun Xu Date: Wed, 24 Dec 2014 09:37:01 +0000 (+0800) Subject: ASoC: rockchip: i2s: set TDL and RDL to 16 samples X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bba1431211e6fdc56680d98d2bdabaab1fd13b79;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git ASoC: rockchip: i2s: set TDL and RDL to 16 samples Set Transmit Data Level(TDL) and Receive Data Level(RDL) to 16 samples. Without this setting, the TDL is default to be 0x00 (means 0 sample), and the RDL is default to be 0x1f (means 32 samples). Signed-off-by: Jianqun Xu Signed-off-by: Mark Brown --- diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 26ec5117b35c..dac0002aad6a 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -247,6 +247,10 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val); regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val); + regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, + I2S_DMACR_TDL(16)); + regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, + I2S_DMACR_RDL(16)); return 0; }