From: Tony Luck Date: Mon, 18 May 2015 20:39:06 +0000 (-0300) Subject: sb_edac: Fix a typo and a thinko in address handling for Haswell X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bb89e7141a4e5690a046d3bdfa57b8521aab64b0;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git sb_edac: Fix a typo and a thinko in address handling for Haswell typo: "a7mode" chooses whether to use bits {8, 7, 9} or {8, 7, 6} in the algorithm to spread access between memory resources. But the non-a7mode path was incorrectly using GET_BITFIELD(addr, 7, 9) and so picking bits {9, 8, 7} thinko: BIT(1) of the dram_rule registers chooses whether to just use the {8, 7, 6} (or {8, 7, 9}) bits mentioned above as they are, or to XOR them with bits {18, 17, 16} but the code inverted the test. We need the additional XOR when dram_rule{1} == 0. Signed-off-by: Tony Luck Acked-by: Aristeu Rozanski Signed-off-by: Mauro Carvalho Chehab --- diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 1acf57ba4c86..b9648323106b 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -1242,9 +1242,9 @@ static int get_memory_error_data(struct mem_ctl_info *mci, bits = GET_BITFIELD(addr, 7, 8) << 1; bits |= GET_BITFIELD(addr, 9, 9); } else - bits = GET_BITFIELD(addr, 7, 9); + bits = GET_BITFIELD(addr, 6, 8); - if (interleave_mode) { + if (interleave_mode == 0) { /* interleave mode will XOR {8,7,6} with {18,17,16} */ idx = GET_BITFIELD(addr, 16, 18); idx ^= bits;