From: Icenowy Zheng Date: Tue, 13 Dec 2016 15:22:48 +0000 (+0800) Subject: clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=bb021cda2ccf45ee9470bf0f8c55323ad1c761ae;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index e1dc4e5b34e1..94f1c8beda8d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);