From: Stefan Roese Date: Thu, 27 Mar 2008 15:34:50 +0000 (+1100) Subject: [POWERPC] 4xx: Only reset PCIe PHY on 405EX systems when no link is detected X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b64c4c937daaa04a0a5c188718fb77e8041b5686;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git [POWERPC] 4xx: Only reset PCIe PHY on 405EX systems when no link is detected Since the arch/powerpc PCI subsystem now does a complete re-assignment of the resources, we can move from the unconditional PCIe PHY reset to the conditional version. Now the PHY is only reset, if no link is established yet. An additional PHY reset (one is already done in U-Boot) leads to problems with some Atheros PCIe boards and some HP FPGA PCIe designs. Signed-off-by: Stefan Roese Signed-off-by: Josh Boyer --- diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 6c925b7975f9..aa856ea9fed8 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c @@ -940,17 +940,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) * PCIe boards don't show this problem. * This has to be re-tested and fixed in a later release! */ -#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources - * configured as done previously by U-Boot. Then Linux will currently - * not reassign them. So the PHY reset is now done always. This will - * lead to problems with the Atheros PCIe board again. - */ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); if (!(val & 0x00001000)) ppc405ex_pcie_phy_reset(port); -#else - ppc405ex_pcie_phy_reset(port); -#endif dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */