From: Roland Vossen <rvossen@broadcom.com>
Date: Wed, 1 Jun 2011 11:45:56 +0000 (+0200)
Subject: staging: brcm80211: further simplified register access macro's
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b61a4be59b7df9c2cee72156fa2958b6ab0fe666;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git

staging: brcm80211: further simplified register access macro's

The SELECT_BUS_READ and SELECT_BUS_WRITE macro's always select
a (sdio) bus operation for fullmac, and a memory operation for
softmac. Thus they can be removed by expanding them in place.

Signed-off-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
---

diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
index 8eeefb41e9a6..acf2a55d1a0f 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
@@ -39,102 +39,30 @@
 #endif
 #endif
 
-#if defined(BCMSDIO)
-#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op
-#define SELECT_BUS_READ(mmap_op, bus_op) bus_op
-#else
-#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op
-#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op
-#endif
-
 /* register access macros */
 #ifndef __BIG_ENDIAN
 #ifndef __mips__
-#define R_REG(r) (\
-	SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
-	readb((volatile u8*)(r)) : \
-	sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
-	readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
-)
+#define R_REG(r) \
+	bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
 #else				/* __mips__ */
-#define R_REG(r) (\
-	SELECT_BUS_READ( \
-		({ \
-			__typeof(*(r)) __osl_v; \
-			__asm__ __volatile__("sync"); \
-			switch (sizeof(*(r))) { \
-			case sizeof(u8): \
-				__osl_v = readb((volatile u8*)(r)); \
-				break; \
-			case sizeof(u16): \
-				__osl_v = readw((volatile u16*)(r)); \
-				break; \
-			case sizeof(u32): \
-				__osl_v = \
-				readl((volatile u32*)(r)); \
-				break; \
-			} \
-			__asm__ __volatile__("sync"); \
-			__osl_v; \
-		}), \
-		({ \
-			__typeof(*(r)) __osl_v; \
-			__asm__ __volatile__("sync"); \
-			__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
-			__asm__ __volatile__("sync"); \
-			__osl_v; \
-		})) \
-)
+#define R_REG(r) \
+	({ \
+		__typeof(*(r)) __osl_v; \
+		__asm__ __volatile__("sync"); \
+		__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
+		__asm__ __volatile__("sync"); \
+		__osl_v; \
+	})
 #endif				/* __mips__ */
 
 #define W_REG(r, v) do { \
-	SELECT_BUS_WRITE( \
-		switch (sizeof(*(r))) { \
-		case sizeof(u8): \
-			writeb((u8)(v), (volatile u8*)(r)); break; \
-		case sizeof(u16): \
-			writew((u16)(v), (volatile u16*)(r)); break; \
-		case sizeof(u32): \
-			writel((u32)(v), (volatile u32*)(r)); break; \
-		}, \
-		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \
+		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v)); \
 	} while (0)
 #else				/* __BIG_ENDIAN */
-#define R_REG(r) (\
-	SELECT_BUS_READ( \
-		({ \
-			__typeof(*(r)) __osl_v; \
-			switch (sizeof(*(r))) { \
-			case sizeof(u8): \
-				__osl_v = \
-				readb((volatile u8*)((r)^3)); \
-				break; \
-			case sizeof(u16): \
-				__osl_v = \
-				readw((volatile u16*)((r)^2)); \
-				break; \
-			case sizeof(u32): \
-				__osl_v = readl((volatile u32*)(r)); \
-				break; \
-			} \
-			__osl_v; \
-		}), \
-		bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
-)
+#define R_REG(r) \
+	bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
 #define W_REG(r, v) do { \
-	SELECT_BUS_WRITE( \
-		switch (sizeof(*(r))) { \
-		case sizeof(u8):	\
-			writeb((u8)(v), \
-			(volatile u8*)((r)^3)); break; \
-		case sizeof(u16):	\
-			writew((u16)(v), \
-			(volatile u16*)((r)^2)); break; \
-		case sizeof(u32):	\
-			writel((u32)(v), \
-			(volatile u32*)(r)); break; \
-		}, \
-		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \
+		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v); \
 	} while (0)
 #endif				/* __BIG_ENDIAN */
 
@@ -155,8 +83,6 @@
 #define SET_REG(r, mask, val) \
 		W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
 
-
-
 #ifdef DHD_DEBUG
 
 /* ARM trap handling */
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_types.h b/drivers/staging/brcm80211/brcmsmac/wlc_types.h
index 12c35bd3a511..059dc17b429d 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_types.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_types.h
@@ -48,56 +48,39 @@ do {						\
 #endif
 #endif
 
-#if defined(BCMSDIO)
-#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op
-#define SELECT_BUS_READ(mmap_op, bus_op) bus_op
-#else
-#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op
-#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op
-#endif
-
 /* register access macros */
 #ifndef __BIG_ENDIAN
 #ifndef __mips__
-#define R_REG(r) (\
-	SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
-	readb((volatile u8*)(r)) : \
-	sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
-	readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
-)
+#define R_REG(r) \
+	({\
+		sizeof(*(r)) == sizeof(u8) ? \
+		readb((volatile u8*)(r)) : \
+		sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
+		readl((volatile u32*)(r)); \
+	})
 #else				/* __mips__ */
-#define R_REG(r) (\
-	SELECT_BUS_READ( \
-		({ \
-			__typeof(*(r)) __osl_v; \
-			__asm__ __volatile__("sync"); \
-			switch (sizeof(*(r))) { \
-			case sizeof(u8): \
-				__osl_v = readb((volatile u8*)(r)); \
-				break; \
-			case sizeof(u16): \
-				__osl_v = readw((volatile u16*)(r)); \
-				break; \
-			case sizeof(u32): \
-				__osl_v = \
-				readl((volatile u32*)(r)); \
-				break; \
-			} \
-			__asm__ __volatile__("sync"); \
-			__osl_v; \
-		}), \
-		({ \
-			__typeof(*(r)) __osl_v; \
-			__asm__ __volatile__("sync"); \
-			__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
-			__asm__ __volatile__("sync"); \
-			__osl_v; \
-		})) \
-)
+#define R_REG(r) \
+	({ \
+		__typeof(*(r)) __osl_v; \
+		__asm__ __volatile__("sync"); \
+		switch (sizeof(*(r))) { \
+		case sizeof(u8): \
+			__osl_v = readb((volatile u8*)(r)); \
+			break; \
+		case sizeof(u16): \
+			__osl_v = readw((volatile u16*)(r)); \
+			break; \
+		case sizeof(u32): \
+			__osl_v = \
+			readl((volatile u32*)(r)); \
+			break; \
+		} \
+		__asm__ __volatile__("sync"); \
+		__osl_v; \
+	})
 #endif				/* __mips__ */
 
 #define W_REG(r, v) do { \
-	SELECT_BUS_WRITE( \
 		switch (sizeof(*(r))) { \
 		case sizeof(u8): \
 			writeb((u8)(v), (volatile u8*)(r)); break; \
@@ -105,33 +88,29 @@ do {						\
 			writew((u16)(v), (volatile u16*)(r)); break; \
 		case sizeof(u32): \
 			writel((u32)(v), (volatile u32*)(r)); break; \
-		}, \
-		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \
+		}; \
 	} while (0)
 #else				/* __BIG_ENDIAN */
-#define R_REG(r) (\
-	SELECT_BUS_READ( \
-		({ \
-			__typeof(*(r)) __osl_v; \
-			switch (sizeof(*(r))) { \
-			case sizeof(u8): \
-				__osl_v = \
-				readb((volatile u8*)((r)^3)); \
-				break; \
-			case sizeof(u16): \
-				__osl_v = \
-				readw((volatile u16*)((r)^2)); \
-				break; \
-			case sizeof(u32): \
-				__osl_v = readl((volatile u32*)(r)); \
-				break; \
-			} \
-			__osl_v; \
-		}), \
-		bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
-)
+#define R_REG(r) \
+	({ \
+		__typeof(*(r)) __osl_v; \
+		switch (sizeof(*(r))) { \
+		case sizeof(u8): \
+			__osl_v = \
+			readb((volatile u8*)((r)^3)); \
+			break; \
+		case sizeof(u16): \
+			__osl_v = \
+			readw((volatile u16*)((r)^2)); \
+			break; \
+		case sizeof(u32): \
+			__osl_v = readl((volatile u32*)(r)); \
+			break; \
+		} \
+		__osl_v; \
+	})
+
 #define W_REG(r, v) do { \
-	SELECT_BUS_WRITE( \
 		switch (sizeof(*(r))) { \
 		case sizeof(u8):	\
 			writeb((u8)(v), \
@@ -142,8 +121,7 @@ do {						\
 		case sizeof(u32):	\
 			writel((u32)(v), \
 			(volatile u32*)(r)); break; \
-		}, \
-		bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \
+		} \
 	} while (0)
 #endif				/* __BIG_ENDIAN */