From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Tue, 12 Jan 2016 19:08:31 +0000 (+0200)
Subject: drm/i915: Pass modifier instead of tiling_mode to gen4_compute_page_offset()
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b5c653384f84b0ccb97e9cf942b6e8ed759221bf;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/i915: Pass modifier instead of tiling_mode to gen4_compute_page_offset()

In preparation for handling more than X tiling, pass the fb modifier to
gen4_compute_page_offset() instead of the obj->tiling_mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1452625717-9713-2-git-send-email-ville.syrjala@linux.intel.com
---

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b79981735c8..e39c724aca89 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2449,11 +2449,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
  * is assumed to be a power-of-two. */
 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
 					     int *x, int *y,
-					     unsigned int tiling_mode,
+					     uint64_t fb_modifier,
 					     unsigned int cpp,
 					     unsigned int pitch)
 {
-	if (tiling_mode != I915_TILING_NONE) {
+	if (fb_modifier != DRM_FORMAT_MOD_NONE) {
 		unsigned int tile_rows, tiles;
 
 		tile_rows = *y / 8;
@@ -2769,8 +2769,8 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_page_offset(dev_priv,
-						       &x, &y, obj->tiling_mode,
+			intel_gen4_compute_page_offset(dev_priv, &x, &y,
+						       fb->modifier[0],
 						       pixel_size,
 						       fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2877,8 +2877,8 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(dev_priv,
-					       &x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(dev_priv, &x, &y,
+					       fb->modifier[0],
 					       pixel_size,
 					       fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e27954d2edad..015538287171 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1198,8 +1198,8 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
 					     int *x, int *y,
-					     unsigned int tiling_mode,
-					     unsigned int bpp,
+					     uint64_t fb_modifier,
+					     unsigned int cpp,
 					     unsigned int pitch);
 void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 73dfb38886b9..3c596c9f0305 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -422,9 +422,8 @@ vlv_update_plane(struct drm_plane *dplane,
 	crtc_h--;
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
-	sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
-							&x, &y,
-							obj->tiling_mode,
+	sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
+							fb->modifier[0],
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
@@ -557,10 +556,10 @@ ivb_update_plane(struct drm_plane *plane,
 		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
-	sprsurf_offset =
-		intel_gen4_compute_page_offset(dev_priv,
-					       &x, &y, obj->tiling_mode,
-					       pixel_size, fb->pitches[0]);
+	sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
+							fb->modifier[0],
+							pixel_size,
+							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
 	if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -696,10 +695,10 @@ ilk_update_plane(struct drm_plane *plane,
 		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
-	dvssurf_offset =
-		intel_gen4_compute_page_offset(dev_priv,
-					       &x, &y, obj->tiling_mode,
-					       pixel_size, fb->pitches[0]);
+	dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
+							fb->modifier[0],
+							pixel_size,
+							fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
 	if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {