From: Simon Horman Date: Wed, 10 May 2017 09:25:29 +0000 (+0200) Subject: mmc: renesas-sdhi: rename sh_mobile_sdhi.c => renesas_sdhi_core.c X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b5b6a5f4f06c0624886b2166e2e8580327f0b943;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git mmc: renesas-sdhi: rename sh_mobile_sdhi.c => renesas_sdhi_core.c Rename the source file SDHI. A follow-up patch will make it a library file used by a different top-level module file. The name "renesas" is chosen as the SDHI driver is applicable to a wider range of SoCs than SH-Mobile it seems to be a more appropriate name. However, the SDHI driver source itself, is left as sh_mobile_sdhi to avoid unnecessary churn. the name "core" was chosen to reflect the desired role of this file, to provide core functionality to the sdhi driver. A follow-up patch will move the file into that role. Internal symbols have also been renamed to reflect the filename change. The .name member of struct platform_driver and parameter to MODULE_ALIAS() have not been changed in order to avoid the complication of potentially breaking SH SoCs which still use platform drivers. Signed-off-by: Simon Horman Acked-by: Arnd Bergmann Reviewed-by: Wolfram Sang Signed-off-by: Ulf Hansson --- diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index e7d3b097cd30..5755b69f2f72 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -571,13 +571,13 @@ config MMC_TMIO T7L66XB and also HTC ASIC3 config MMC_SDHI - tristate "SH-Mobile SDHI SD/SDIO controller support" + tristate "Renesas SDHI SD/SDIO controller support" depends on SUPERH || ARM || ARM64 depends on SUPERH || ARCH_RENESAS || COMPILE_TEST select MMC_TMIO_CORE help This provides support for the SDHI SD/SDIO controller found in - SuperH and ARM SH-Mobile SoCs + Renesas SuperH, ARM and ARM64 based SoCs config MMC_CB710 tristate "ENE CB710 MMC/SD Interface support" diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 15e3cdcda673..4d4547116311 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -36,7 +36,7 @@ obj-$(CONFIG_MMC_S3C) += s3cmci.o obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o obj-$(CONFIG_MMC_TMIO_CORE) += tmio_mmc_core.o -obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o renesas_sdhi_sys_dmac.o +obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_core.o renesas_sdhi_sys_dmac.o obj-$(CONFIG_MMC_CB710) += cb710-mmc.o obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c new file mode 100644 index 000000000000..b605b8fe9499 --- /dev/null +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -0,0 +1,770 @@ +/* + * SuperH Mobile SDHI + * + * Copyright (C) 2016 Sang Engineering, Wolfram Sang + * Copyright (C) 2015-16 Renesas Electronics Corporation + * Copyright (C) 2009 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Based on "Compaq ASIC3 support": + * + * Copyright 2001 Compaq Computer Corporation. + * Copyright 2004-2005 Phil Blundell + * Copyright 2007-2008 OpenedHand Ltd. + * + * Authors: Phil Blundell , + * Samuel Ortiz + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "renesas_sdhi.h" +#include "tmio_mmc.h" + +#define EXT_ACC 0xe4 + +#define SDHI_VER_GEN2_SDR50 0x490c +/* very old datasheets said 0x490c for SDR104, too. They are wrong! */ +#define SDHI_VER_GEN2_SDR104 0xcb0d +#define SDHI_VER_GEN3_SD 0xcc10 +#define SDHI_VER_GEN3_SDMMC 0xcd10 + +#define host_to_priv(host) container_of((host)->pdata, struct renesas_sdhi, mmc_data) + +struct renesas_sdhi_scc { + unsigned long clk_rate; /* clock rate for SDR104 */ + u32 tap; /* sampling clock position for SDR104 */ +}; + +struct renesas_sdhi_of_data { + unsigned long tmio_flags; + u32 tmio_ocr_mask; + unsigned long capabilities; + unsigned long capabilities2; + enum dma_slave_buswidth dma_buswidth; + dma_addr_t dma_rx_offset; + unsigned bus_shift; + int scc_offset; + struct renesas_sdhi_scc *taps; + int taps_num; +}; + +static const struct renesas_sdhi_of_data of_default_cfg = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, +}; + +static const struct renesas_sdhi_of_data of_rz_compatible = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT, + .tmio_ocr_mask = MMC_VDD_32_33, + .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, +}; + +static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | + TMIO_MMC_CLK_ACTUAL, + .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, +}; + +/* Definitions for sampling clocks */ +static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = { + { + .clk_rate = 156000000, + .tap = 0x00000703, + }, + { + .clk_rate = 0, + .tap = 0x00000300, + }, +}; + +static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | + TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2, + .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES, + .dma_rx_offset = 0x2000, + .scc_offset = 0x0300, + .taps = rcar_gen2_scc_taps, + .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps), +}; + +/* Definitions for sampling clocks */ +static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { + { + .clk_rate = 0, + .tap = 0x00000300, + }, +}; + +static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | + TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2, + .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + .bus_shift = 2, + .scc_offset = 0x1000, + .taps = rcar_gen3_scc_taps, + .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), +}; + +static const struct of_device_id renesas_sdhi_of_match[] = { + { .compatible = "renesas,sdhi-shmobile" }, + { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, }, + { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, }, + { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, }, + { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, }, + { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, }, + { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, }, + { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, }, + { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, }, + { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, }, + { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, }, + { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, }, + { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, + { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, + {}, +}; +MODULE_DEVICE_TABLE(of, renesas_sdhi_of_match); + +struct renesas_sdhi { + struct clk *clk; + struct clk *clk_cd; + struct tmio_mmc_data mmc_data; + struct tmio_mmc_dma dma_priv; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default, *pins_uhs; + void __iomem *scc_ctl; +}; + +static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) +{ + u32 val; + + /* + * see also + * renesas_sdhi_of_data :: dma_buswidth + */ + switch (sd_ctrl_read16(host, CTL_VERSION)) { + case SDHI_VER_GEN2_SDR50: + val = (width == 32) ? 0x0001 : 0x0000; + break; + case SDHI_VER_GEN2_SDR104: + val = (width == 32) ? 0x0000 : 0x0001; + break; + case SDHI_VER_GEN3_SD: + case SDHI_VER_GEN3_SDMMC: + if (width == 64) + val = 0x0000; + else if (width == 32) + val = 0x0101; + else + val = 0x0001; + break; + default: + /* nothing to do */ + return; + } + + sd_ctrl_write16(host, EXT_ACC, val); +} + +static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) +{ + struct mmc_host *mmc = host->mmc; + struct renesas_sdhi *priv = host_to_priv(host); + int ret = clk_prepare_enable(priv->clk); + if (ret < 0) + return ret; + + ret = clk_prepare_enable(priv->clk_cd); + if (ret < 0) { + clk_disable_unprepare(priv->clk); + return ret; + } + + /* + * The clock driver may not know what maximum frequency + * actually works, so it should be set with the max-frequency + * property which will already have been read to f_max. If it + * was missing, assume the current frequency is the maximum. + */ + if (!mmc->f_max) + mmc->f_max = clk_get_rate(priv->clk); + + /* + * Minimum frequency is the minimum input clock frequency + * divided by our maximum divider. + */ + mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); + + /* enable 16bit data access on SDBUF as default */ + renesas_sdhi_sdbuf_width(host, 16); + + return 0; +} + +static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + struct renesas_sdhi *priv = host_to_priv(host); + unsigned int freq, diff, best_freq = 0, diff_min = ~0; + int i, ret; + + /* tested only on RCar Gen2+ currently; may work for others */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + return clk_get_rate(priv->clk); + + /* + * We want the bus clock to be as close as possible to, but no + * greater than, new_clock. As we can divide by 1 << i for + * any i in [0, 9] we want the input clock to be as close as + * possible, but no greater than, new_clock << i. + */ + for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { + freq = clk_round_rate(priv->clk, new_clock << i); + if (freq > (new_clock << i)) { + /* Too fast; look for a slightly slower option */ + freq = clk_round_rate(priv->clk, + (new_clock << i) / 4 * 3); + if (freq > (new_clock << i)) + continue; + } + + diff = new_clock - (freq >> i); + if (diff <= diff_min) { + best_freq = freq; + diff_min = diff; + } + } + + ret = clk_set_rate(priv->clk, best_freq); + + return ret == 0 ? best_freq : clk_get_rate(priv->clk); +} + +static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) +{ + struct renesas_sdhi *priv = host_to_priv(host); + + clk_disable_unprepare(priv->clk); + clk_disable_unprepare(priv->clk_cd); +} + +static int renesas_sdhi_card_busy(struct mmc_host *mmc) +{ + struct tmio_mmc_host *host = mmc_priv(mmc); + + return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_DAT0); +} + +static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct tmio_mmc_host *host = mmc_priv(mmc); + struct renesas_sdhi *priv = host_to_priv(host); + struct pinctrl_state *pin_state; + int ret; + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + pin_state = priv->pins_default; + break; + case MMC_SIGNAL_VOLTAGE_180: + pin_state = priv->pins_uhs; + break; + default: + return -EINVAL; + } + + /* + * If anything is missing, assume signal voltage is fixed at + * 3.3V and succeed/fail accordingly. + */ + if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) + return ios->signal_voltage == + MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; + + ret = mmc_regulator_set_vqmmc(host->mmc, ios); + if (ret) + return ret; + + return pinctrl_select_state(priv->pinctrl, pin_state); +} + +/* SCC registers */ +#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 +#define SH_MOBILE_SDHI_SCC_TAPSET 0x002 +#define SH_MOBILE_SDHI_SCC_DT2FF 0x004 +#define SH_MOBILE_SDHI_SCC_CKSEL 0x006 +#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 +#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A + +/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ +#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) +#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 +#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff + +/* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ +#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) +/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ +#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) +/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ +#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) + +static inline u32 sd_scc_read32(struct tmio_mmc_host *host, + struct renesas_sdhi *priv, int addr) +{ + return readl(priv->scc_ctl + (addr << host->bus_shift)); +} + +static inline void sd_scc_write32(struct tmio_mmc_host *host, + struct renesas_sdhi *priv, + int addr, u32 val) +{ + writel(val, priv->scc_ctl + (addr << host->bus_shift)); +} + +static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) +{ + struct renesas_sdhi *priv; + + priv = host_to_priv(host); + + /* set sampling clock selection range */ + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, + 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); + + /* Initialize SCC */ + sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, + SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, + SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, + ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos); + + /* Read TAPNUM */ + return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> + SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & + SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; +} + +static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, + unsigned long tap) +{ + struct renesas_sdhi *priv = host_to_priv(host); + + /* Set sampling clock position */ + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); +} + +#define SH_MOBILE_SDHI_MAX_TAP 3 + +static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) +{ + struct renesas_sdhi *priv = host_to_priv(host); + unsigned long tap_cnt; /* counter of tuning success */ + unsigned long tap_set; /* tap position */ + unsigned long tap_start;/* start position of tuning success */ + unsigned long tap_end; /* end position of tuning success */ + unsigned long ntap; /* temporary counter of tuning success */ + unsigned long i; + + /* Clear SCC_RVSREQ */ + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); + + /* + * Find the longest consecutive run of successful probes. If that + * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the + * center index as the tap. + */ + tap_cnt = 0; + ntap = 0; + tap_start = 0; + tap_end = 0; + for (i = 0; i < host->tap_num * 2; i++) { + if (test_bit(i, host->taps)) + ntap++; + else { + if (ntap > tap_cnt) { + tap_start = i - ntap; + tap_end = i - 1; + tap_cnt = ntap; + } + ntap = 0; + } + } + + if (ntap > tap_cnt) { + tap_start = i - ntap; + tap_end = i - 1; + tap_cnt = ntap; + } + + if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) + tap_set = (tap_start + tap_end) / 2 % host->tap_num; + else + return -EIO; + + /* Set SCC */ + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set); + + /* Enable auto re-tuning */ + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, + SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); + + return 0; +} + + +static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) +{ + struct renesas_sdhi *priv = host_to_priv(host); + + /* Check SCC error */ + if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & + SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & + SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { + /* Clear SCC error */ + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); + return true; + } + + return false; +} + +static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) +{ + struct renesas_sdhi *priv; + + priv = host_to_priv(host); + + /* Reset SCC */ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, + ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, + ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, + ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); +} + +static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host) +{ + int timeout = 1000; + + while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) + & TMIO_STAT_SCLKDIVEN)) + udelay(1); + + if (!timeout) { + dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); + return -EBUSY; + } + + return 0; +} + +static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) +{ + switch (addr) + { + case CTL_SD_CMD: + case CTL_STOP_INTERNAL_ACTION: + case CTL_XFER_BLK_COUNT: + case CTL_SD_CARD_CLK_CTL: + case CTL_SD_XFER_LEN: + case CTL_SD_MEM_CARD_OPT: + case CTL_TRANSACTION_CTL: + case CTL_DMA_ENABLE: + case EXT_ACC: + return renesas_sdhi_wait_idle(host); + } + + return 0; +} + +static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, + unsigned int direction, int blk_size) +{ + /* + * In Renesas controllers, when performing a + * multiple block read of one or two blocks, + * depending on the timing with which the + * response register is read, the response + * value may not be read properly. + * Use single block read for this HW bug + */ + if ((direction == MMC_DATA_READ) && + blk_size == 2) + return 1; + + return blk_size; +} + +static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) +{ + sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0); + + /* enable 32bit access if DMA mode if possibile */ + renesas_sdhi_sdbuf_width(host, enable ? 32 : 16); +} + +static int renesas_sdhi_probe(struct platform_device *pdev) +{ + const struct renesas_sdhi_of_data *of_data = of_device_get_match_data(&pdev->dev); + struct renesas_sdhi *priv; + struct tmio_mmc_data *mmc_data; + struct tmio_mmc_data *mmd = pdev->dev.platform_data; + struct tmio_mmc_host *host; + struct resource *res; + int irq, ret, i; + struct tmio_mmc_dma *dma_priv; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mmc_data = &priv->mmc_data; + dma_priv = &priv->dma_priv; + + priv->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) { + ret = PTR_ERR(priv->clk); + dev_err(&pdev->dev, "cannot get clock: %d\n", ret); + goto eprobe; + } + + /* + * Some controllers provide a 2nd clock just to run the internal card + * detection logic. Unfortunately, the existing driver architecture does + * not support a separation of clocks for runtime PM usage. When + * native hotplug is used, the tmio driver assumes that the core + * must continue to run for card detect to stay active, so we cannot + * disable it. + * Additionally, it is prohibited to supply a clock to the core but not + * to the card detect circuit. That leaves us with if separate clocks + * are presented, we must treat them both as virtually 1 clock. + */ + priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); + if (IS_ERR(priv->clk_cd)) + priv->clk_cd = NULL; + + priv->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!IS_ERR(priv->pinctrl)) { + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, + PINCTRL_STATE_DEFAULT); + priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, + "state_uhs"); + } + + host = tmio_mmc_host_alloc(pdev); + if (!host) { + ret = -ENOMEM; + goto eprobe; + } + + + if (of_data) { + mmc_data->flags |= of_data->tmio_flags; + mmc_data->ocr_mask = of_data->tmio_ocr_mask; + mmc_data->capabilities |= of_data->capabilities; + mmc_data->capabilities2 |= of_data->capabilities2; + mmc_data->dma_rx_offset = of_data->dma_rx_offset; + dma_priv->dma_buswidth = of_data->dma_buswidth; + host->bus_shift = of_data->bus_shift; + } + + host->dma = dma_priv; + host->write16_hook = renesas_sdhi_write16_hook; + host->clk_enable = renesas_sdhi_clk_enable; + host->clk_update = renesas_sdhi_clk_update; + host->clk_disable = renesas_sdhi_clk_disable; + host->multi_io_quirk = renesas_sdhi_multi_io_quirk; + + /* SDR speeds are only available on Gen2+ */ + if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { + /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ + host->card_busy = renesas_sdhi_card_busy; + host->start_signal_voltage_switch = + renesas_sdhi_start_signal_voltage_switch; + } + + /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ + if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ + host->bus_shift = 1; + + if (mmd) + *mmc_data = *mmd; + + dma_priv->filter = shdma_chan_filter; + dma_priv->enable = renesas_sdhi_enable_dma; + + mmc_data->alignment_shift = 1; /* 2-byte alignment */ + mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; + + /* + * All SDHI blocks support 2-byte and larger block sizes in 4-bit + * bus width mode. + */ + mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; + + /* + * All SDHI blocks support SDIO IRQ signalling. + */ + mmc_data->flags |= TMIO_MMC_SDIO_IRQ; + + /* + * All SDHI have CMD12 controll bit + */ + mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; + + /* All SDHI have SDIO status bits which must be 1 */ + mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; + + ret = tmio_mmc_host_probe(host, mmc_data, renesas_sdhi_get_dma_ops()); + if (ret < 0) + goto efree; + + /* Enable tuning iff we have an SCC and a supported mode */ + if (of_data && of_data->scc_offset && + (host->mmc->caps & MMC_CAP_UHS_SDR104 || + host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { + const struct renesas_sdhi_scc *taps = of_data->taps; + bool hit = false; + + host->mmc->caps |= MMC_CAP_HW_RESET; + + for (i = 0; i < of_data->taps_num; i++) { + if (taps[i].clk_rate == 0 || + taps[i].clk_rate == host->mmc->f_max) { + host->scc_tappos = taps->tap; + hit = true; + break; + } + } + + if (!hit) + dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); + + priv->scc_ctl = host->ctl + of_data->scc_offset; + host->init_tuning = renesas_sdhi_init_tuning; + host->prepare_tuning = renesas_sdhi_prepare_tuning; + host->select_tuning = renesas_sdhi_select_tuning; + host->check_scc_error = renesas_sdhi_check_scc_error; + host->hw_reset = renesas_sdhi_hw_reset; + } + + i = 0; + while (1) { + irq = platform_get_irq(pdev, i); + if (irq < 0) + break; + i++; + ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, + dev_name(&pdev->dev), host); + if (ret) + goto eirq; + } + + /* There must be at least one IRQ source */ + if (!i) { + ret = irq; + goto eirq; + } + + dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", + mmc_hostname(host->mmc), (unsigned long) + (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), + host->mmc->f_max / 1000000); + + return ret; + +eirq: + tmio_mmc_host_remove(host); +efree: + tmio_mmc_host_free(host); +eprobe: + return ret; +} + +static int renesas_sdhi_remove(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct tmio_mmc_host *host = mmc_priv(mmc); + + tmio_mmc_host_remove(host); + + return 0; +} + +static const struct dev_pm_ops tmio_mmc_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, + tmio_mmc_host_runtime_resume, + NULL) +}; + +static struct platform_driver renesas_sdhi_driver = { + .driver = { + .name = "sh_mobile_sdhi", + .pm = &tmio_mmc_dev_pm_ops, + .of_match_table = renesas_sdhi_of_match, + }, + .probe = renesas_sdhi_probe, + .remove = renesas_sdhi_remove, +}; + +module_platform_driver(renesas_sdhi_driver); + +MODULE_DESCRIPTION("Renesas SDHI driver"); +MODULE_AUTHOR("Magnus Damm"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sh_mobile_sdhi"); diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c deleted file mode 100644 index 708c2ba28f99..000000000000 --- a/drivers/mmc/host/sh_mobile_sdhi.c +++ /dev/null @@ -1,770 +0,0 @@ -/* - * SuperH Mobile SDHI - * - * Copyright (C) 2016 Sang Engineering, Wolfram Sang - * Copyright (C) 2015-16 Renesas Electronics Corporation - * Copyright (C) 2009 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Based on "Compaq ASIC3 support": - * - * Copyright 2001 Compaq Computer Corporation. - * Copyright 2004-2005 Phil Blundell - * Copyright 2007-2008 OpenedHand Ltd. - * - * Authors: Phil Blundell , - * Samuel Ortiz - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "renesas_sdhi.h" -#include "tmio_mmc.h" - -#define EXT_ACC 0xe4 - -#define SDHI_VER_GEN2_SDR50 0x490c -/* very old datasheets said 0x490c for SDR104, too. They are wrong! */ -#define SDHI_VER_GEN2_SDR104 0xcb0d -#define SDHI_VER_GEN3_SD 0xcc10 -#define SDHI_VER_GEN3_SDMMC 0xcd10 - -#define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data) - -struct sh_mobile_sdhi_scc { - unsigned long clk_rate; /* clock rate for SDR104 */ - u32 tap; /* sampling clock position for SDR104 */ -}; - -struct sh_mobile_sdhi_of_data { - unsigned long tmio_flags; - u32 tmio_ocr_mask; - unsigned long capabilities; - unsigned long capabilities2; - enum dma_slave_buswidth dma_buswidth; - dma_addr_t dma_rx_offset; - unsigned bus_shift; - int scc_offset; - struct sh_mobile_sdhi_scc *taps; - int taps_num; -}; - -static const struct sh_mobile_sdhi_of_data of_default_cfg = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, -}; - -static const struct sh_mobile_sdhi_of_data of_rz_compatible = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT, - .tmio_ocr_mask = MMC_VDD_32_33, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, -}; - -static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | - TMIO_MMC_CLK_ACTUAL, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, -}; - -/* Definitions for sampling clocks */ -static struct sh_mobile_sdhi_scc rcar_gen2_scc_taps[] = { - { - .clk_rate = 156000000, - .tap = 0x00000703, - }, - { - .clk_rate = 0, - .tap = 0x00000300, - }, -}; - -static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | - TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES, - .dma_rx_offset = 0x2000, - .scc_offset = 0x0300, - .taps = rcar_gen2_scc_taps, - .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps), -}; - -/* Definitions for sampling clocks */ -static struct sh_mobile_sdhi_scc rcar_gen3_scc_taps[] = { - { - .clk_rate = 0, - .tap = 0x00000300, - }, -}; - -static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE | - TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2, - .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .bus_shift = 2, - .scc_offset = 0x1000, - .taps = rcar_gen3_scc_taps, - .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), -}; - -static const struct of_device_id sh_mobile_sdhi_of_match[] = { - { .compatible = "renesas,sdhi-shmobile" }, - { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, }, - { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, }, - { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, }, - { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, }, - { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, }, - { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, }, - { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, }, - { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, }, - { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, }, - { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, }, - { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, }, - { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, - { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, - {}, -}; -MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match); - -struct sh_mobile_sdhi { - struct clk *clk; - struct clk *clk_cd; - struct tmio_mmc_data mmc_data; - struct tmio_mmc_dma dma_priv; - struct pinctrl *pinctrl; - struct pinctrl_state *pins_default, *pins_uhs; - void __iomem *scc_ctl; -}; - -static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) -{ - u32 val; - - /* - * see also - * sh_mobile_sdhi_of_data :: dma_buswidth - */ - switch (sd_ctrl_read16(host, CTL_VERSION)) { - case SDHI_VER_GEN2_SDR50: - val = (width == 32) ? 0x0001 : 0x0000; - break; - case SDHI_VER_GEN2_SDR104: - val = (width == 32) ? 0x0000 : 0x0001; - break; - case SDHI_VER_GEN3_SD: - case SDHI_VER_GEN3_SDMMC: - if (width == 64) - val = 0x0000; - else if (width == 32) - val = 0x0101; - else - val = 0x0001; - break; - default: - /* nothing to do */ - return; - } - - sd_ctrl_write16(host, EXT_ACC, val); -} - -static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host) -{ - struct mmc_host *mmc = host->mmc; - struct sh_mobile_sdhi *priv = host_to_priv(host); - int ret = clk_prepare_enable(priv->clk); - if (ret < 0) - return ret; - - ret = clk_prepare_enable(priv->clk_cd); - if (ret < 0) { - clk_disable_unprepare(priv->clk); - return ret; - } - - /* - * The clock driver may not know what maximum frequency - * actually works, so it should be set with the max-frequency - * property which will already have been read to f_max. If it - * was missing, assume the current frequency is the maximum. - */ - if (!mmc->f_max) - mmc->f_max = clk_get_rate(priv->clk); - - /* - * Minimum frequency is the minimum input clock frequency - * divided by our maximum divider. - */ - mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); - - /* enable 16bit data access on SDBUF as default */ - sh_mobile_sdhi_sdbuf_width(host, 16); - - return 0; -} - -static unsigned int sh_mobile_sdhi_clk_update(struct tmio_mmc_host *host, - unsigned int new_clock) -{ - struct sh_mobile_sdhi *priv = host_to_priv(host); - unsigned int freq, diff, best_freq = 0, diff_min = ~0; - int i, ret; - - /* tested only on RCar Gen2+ currently; may work for others */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - return clk_get_rate(priv->clk); - - /* - * We want the bus clock to be as close as possible to, but no - * greater than, new_clock. As we can divide by 1 << i for - * any i in [0, 9] we want the input clock to be as close as - * possible, but no greater than, new_clock << i. - */ - for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { - freq = clk_round_rate(priv->clk, new_clock << i); - if (freq > (new_clock << i)) { - /* Too fast; look for a slightly slower option */ - freq = clk_round_rate(priv->clk, - (new_clock << i) / 4 * 3); - if (freq > (new_clock << i)) - continue; - } - - diff = new_clock - (freq >> i); - if (diff <= diff_min) { - best_freq = freq; - diff_min = diff; - } - } - - ret = clk_set_rate(priv->clk, best_freq); - - return ret == 0 ? best_freq : clk_get_rate(priv->clk); -} - -static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host) -{ - struct sh_mobile_sdhi *priv = host_to_priv(host); - - clk_disable_unprepare(priv->clk); - clk_disable_unprepare(priv->clk_cd); -} - -static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc) -{ - struct tmio_mmc_host *host = mmc_priv(mmc); - - return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_DAT0); -} - -static int sh_mobile_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, - struct mmc_ios *ios) -{ - struct tmio_mmc_host *host = mmc_priv(mmc); - struct sh_mobile_sdhi *priv = host_to_priv(host); - struct pinctrl_state *pin_state; - int ret; - - switch (ios->signal_voltage) { - case MMC_SIGNAL_VOLTAGE_330: - pin_state = priv->pins_default; - break; - case MMC_SIGNAL_VOLTAGE_180: - pin_state = priv->pins_uhs; - break; - default: - return -EINVAL; - } - - /* - * If anything is missing, assume signal voltage is fixed at - * 3.3V and succeed/fail accordingly. - */ - if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) - return ios->signal_voltage == - MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; - - ret = mmc_regulator_set_vqmmc(host->mmc, ios); - if (ret) - return ret; - - return pinctrl_select_state(priv->pinctrl, pin_state); -} - -/* SCC registers */ -#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 -#define SH_MOBILE_SDHI_SCC_TAPSET 0x002 -#define SH_MOBILE_SDHI_SCC_DT2FF 0x004 -#define SH_MOBILE_SDHI_SCC_CKSEL 0x006 -#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 -#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A - -/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ -#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) -#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 -#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff - -/* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ -#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) -/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ -#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) -/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ -#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) - -static inline u32 sd_scc_read32(struct tmio_mmc_host *host, - struct sh_mobile_sdhi *priv, int addr) -{ - return readl(priv->scc_ctl + (addr << host->bus_shift)); -} - -static inline void sd_scc_write32(struct tmio_mmc_host *host, - struct sh_mobile_sdhi *priv, - int addr, u32 val) -{ - writel(val, priv->scc_ctl + (addr << host->bus_shift)); -} - -static unsigned int sh_mobile_sdhi_init_tuning(struct tmio_mmc_host *host) -{ - struct sh_mobile_sdhi *priv; - - priv = host_to_priv(host); - - /* set sampling clock selection range */ - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, - 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); - - /* Initialize SCC */ - sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, - SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, - SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, - ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos); - - /* Read TAPNUM */ - return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> - SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & - SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; -} - -static void sh_mobile_sdhi_prepare_tuning(struct tmio_mmc_host *host, - unsigned long tap) -{ - struct sh_mobile_sdhi *priv = host_to_priv(host); - - /* Set sampling clock position */ - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); -} - -#define SH_MOBILE_SDHI_MAX_TAP 3 - -static int sh_mobile_sdhi_select_tuning(struct tmio_mmc_host *host) -{ - struct sh_mobile_sdhi *priv = host_to_priv(host); - unsigned long tap_cnt; /* counter of tuning success */ - unsigned long tap_set; /* tap position */ - unsigned long tap_start;/* start position of tuning success */ - unsigned long tap_end; /* end position of tuning success */ - unsigned long ntap; /* temporary counter of tuning success */ - unsigned long i; - - /* Clear SCC_RVSREQ */ - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); - - /* - * Find the longest consecutive run of successful probes. If that - * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the - * center index as the tap. - */ - tap_cnt = 0; - ntap = 0; - tap_start = 0; - tap_end = 0; - for (i = 0; i < host->tap_num * 2; i++) { - if (test_bit(i, host->taps)) - ntap++; - else { - if (ntap > tap_cnt) { - tap_start = i - ntap; - tap_end = i - 1; - tap_cnt = ntap; - } - ntap = 0; - } - } - - if (ntap > tap_cnt) { - tap_start = i - ntap; - tap_end = i - 1; - tap_cnt = ntap; - } - - if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) - tap_set = (tap_start + tap_end) / 2 % host->tap_num; - else - return -EIO; - - /* Set SCC */ - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set); - - /* Enable auto re-tuning */ - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, - SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); - - return 0; -} - - -static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host) -{ - struct sh_mobile_sdhi *priv = host_to_priv(host); - - /* Check SCC error */ - if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & - SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & - SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { - /* Clear SCC error */ - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); - return true; - } - - return false; -} - -static void sh_mobile_sdhi_hw_reset(struct tmio_mmc_host *host) -{ - struct sh_mobile_sdhi *priv; - - priv = host_to_priv(host); - - /* Reset SCC */ - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, - ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, - ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); - - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, - ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); -} - -static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host) -{ - int timeout = 1000; - - while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) - & TMIO_STAT_SCLKDIVEN)) - udelay(1); - - if (!timeout) { - dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); - return -EBUSY; - } - - return 0; -} - -static int sh_mobile_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) -{ - switch (addr) - { - case CTL_SD_CMD: - case CTL_STOP_INTERNAL_ACTION: - case CTL_XFER_BLK_COUNT: - case CTL_SD_CARD_CLK_CTL: - case CTL_SD_XFER_LEN: - case CTL_SD_MEM_CARD_OPT: - case CTL_TRANSACTION_CTL: - case CTL_DMA_ENABLE: - case EXT_ACC: - return sh_mobile_sdhi_wait_idle(host); - } - - return 0; -} - -static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card, - unsigned int direction, int blk_size) -{ - /* - * In Renesas controllers, when performing a - * multiple block read of one or two blocks, - * depending on the timing with which the - * response register is read, the response - * value may not be read properly. - * Use single block read for this HW bug - */ - if ((direction == MMC_DATA_READ) && - blk_size == 2) - return 1; - - return blk_size; -} - -static void sh_mobile_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) -{ - sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0); - - /* enable 32bit access if DMA mode if possibile */ - sh_mobile_sdhi_sdbuf_width(host, enable ? 32 : 16); -} - -static int sh_mobile_sdhi_probe(struct platform_device *pdev) -{ - const struct sh_mobile_sdhi_of_data *of_data = of_device_get_match_data(&pdev->dev); - struct sh_mobile_sdhi *priv; - struct tmio_mmc_data *mmc_data; - struct tmio_mmc_data *mmd = pdev->dev.platform_data; - struct tmio_mmc_host *host; - struct resource *res; - int irq, ret, i; - struct tmio_mmc_dma *dma_priv; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - - priv = devm_kzalloc(&pdev->dev, sizeof(struct sh_mobile_sdhi), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - mmc_data = &priv->mmc_data; - dma_priv = &priv->dma_priv; - - priv->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) { - ret = PTR_ERR(priv->clk); - dev_err(&pdev->dev, "cannot get clock: %d\n", ret); - goto eprobe; - } - - /* - * Some controllers provide a 2nd clock just to run the internal card - * detection logic. Unfortunately, the existing driver architecture does - * not support a separation of clocks for runtime PM usage. When - * native hotplug is used, the tmio driver assumes that the core - * must continue to run for card detect to stay active, so we cannot - * disable it. - * Additionally, it is prohibited to supply a clock to the core but not - * to the card detect circuit. That leaves us with if separate clocks - * are presented, we must treat them both as virtually 1 clock. - */ - priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); - if (IS_ERR(priv->clk_cd)) - priv->clk_cd = NULL; - - priv->pinctrl = devm_pinctrl_get(&pdev->dev); - if (!IS_ERR(priv->pinctrl)) { - priv->pins_default = pinctrl_lookup_state(priv->pinctrl, - PINCTRL_STATE_DEFAULT); - priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, - "state_uhs"); - } - - host = tmio_mmc_host_alloc(pdev); - if (!host) { - ret = -ENOMEM; - goto eprobe; - } - - - if (of_data) { - mmc_data->flags |= of_data->tmio_flags; - mmc_data->ocr_mask = of_data->tmio_ocr_mask; - mmc_data->capabilities |= of_data->capabilities; - mmc_data->capabilities2 |= of_data->capabilities2; - mmc_data->dma_rx_offset = of_data->dma_rx_offset; - dma_priv->dma_buswidth = of_data->dma_buswidth; - host->bus_shift = of_data->bus_shift; - } - - host->dma = dma_priv; - host->write16_hook = sh_mobile_sdhi_write16_hook; - host->clk_enable = sh_mobile_sdhi_clk_enable; - host->clk_update = sh_mobile_sdhi_clk_update; - host->clk_disable = sh_mobile_sdhi_clk_disable; - host->multi_io_quirk = sh_mobile_sdhi_multi_io_quirk; - - /* SDR speeds are only available on Gen2+ */ - if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { - /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ - host->card_busy = sh_mobile_sdhi_card_busy; - host->start_signal_voltage_switch = - sh_mobile_sdhi_start_signal_voltage_switch; - } - - /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ - if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ - host->bus_shift = 1; - - if (mmd) - *mmc_data = *mmd; - - dma_priv->filter = shdma_chan_filter; - dma_priv->enable = sh_mobile_sdhi_enable_dma; - - mmc_data->alignment_shift = 1; /* 2-byte alignment */ - mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; - - /* - * All SDHI blocks support 2-byte and larger block sizes in 4-bit - * bus width mode. - */ - mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; - - /* - * All SDHI blocks support SDIO IRQ signalling. - */ - mmc_data->flags |= TMIO_MMC_SDIO_IRQ; - - /* - * All SDHI have CMD12 controll bit - */ - mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; - - /* All SDHI have SDIO status bits which must be 1 */ - mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; - - ret = tmio_mmc_host_probe(host, mmc_data, renesas_sdhi_get_dma_ops()); - if (ret < 0) - goto efree; - - /* Enable tuning iff we have an SCC and a supported mode */ - if (of_data && of_data->scc_offset && - (host->mmc->caps & MMC_CAP_UHS_SDR104 || - host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { - const struct sh_mobile_sdhi_scc *taps = of_data->taps; - bool hit = false; - - host->mmc->caps |= MMC_CAP_HW_RESET; - - for (i = 0; i < of_data->taps_num; i++) { - if (taps[i].clk_rate == 0 || - taps[i].clk_rate == host->mmc->f_max) { - host->scc_tappos = taps->tap; - hit = true; - break; - } - } - - if (!hit) - dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); - - priv->scc_ctl = host->ctl + of_data->scc_offset; - host->init_tuning = sh_mobile_sdhi_init_tuning; - host->prepare_tuning = sh_mobile_sdhi_prepare_tuning; - host->select_tuning = sh_mobile_sdhi_select_tuning; - host->check_scc_error = sh_mobile_sdhi_check_scc_error; - host->hw_reset = sh_mobile_sdhi_hw_reset; - } - - i = 0; - while (1) { - irq = platform_get_irq(pdev, i); - if (irq < 0) - break; - i++; - ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, - dev_name(&pdev->dev), host); - if (ret) - goto eirq; - } - - /* There must be at least one IRQ source */ - if (!i) { - ret = irq; - goto eirq; - } - - dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", - mmc_hostname(host->mmc), (unsigned long) - (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), - host->mmc->f_max / 1000000); - - return ret; - -eirq: - tmio_mmc_host_remove(host); -efree: - tmio_mmc_host_free(host); -eprobe: - return ret; -} - -static int sh_mobile_sdhi_remove(struct platform_device *pdev) -{ - struct mmc_host *mmc = platform_get_drvdata(pdev); - struct tmio_mmc_host *host = mmc_priv(mmc); - - tmio_mmc_host_remove(host); - - return 0; -} - -static const struct dev_pm_ops tmio_mmc_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, - pm_runtime_force_resume) - SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, - tmio_mmc_host_runtime_resume, - NULL) -}; - -static struct platform_driver sh_mobile_sdhi_driver = { - .driver = { - .name = "sh_mobile_sdhi", - .pm = &tmio_mmc_dev_pm_ops, - .of_match_table = sh_mobile_sdhi_of_match, - }, - .probe = sh_mobile_sdhi_probe, - .remove = sh_mobile_sdhi_remove, -}; - -module_platform_driver(sh_mobile_sdhi_driver); - -MODULE_DESCRIPTION("SuperH Mobile SDHI driver"); -MODULE_AUTHOR("Magnus Damm"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:sh_mobile_sdhi");