From: Ville Syrjälä Date: Tue, 3 Sep 2013 10:31:38 +0000 (+0300) Subject: drm/i915: Kill IRONLAKE_FDI_FREQ check X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b315fedf01ac717f1c2a5eaa6959335b6baf7150;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: Kill IRONLAKE_FDI_FREQ check ironlake_fdi_compute_config() already checks that we have enough FDI bandwidth. And it doesn't just use a hardcoded value but takes into account factors such as the actual FDI frequency, shared FDI B/C lanes, etc. Suggested-by: Daniel Vetter Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d54c9bfeb226..d88057edfdea 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -69,9 +69,6 @@ struct intel_limit { intel_p2_t p2; }; -/* FDI */ -#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ - int intel_pch_rawclk(struct drm_device *dev) { @@ -4107,13 +4104,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; - if (HAS_PCH_SPLIT(dev)) { - /* FDI link clock is fixed at 2.7G */ - if (pipe_config->requested_mode.clock * 3 - > IRONLAKE_FDI_FREQ * 4) - return -EINVAL; - } - /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */