From: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Date: Wed, 2 Dec 2015 16:47:17 +0000 (+0100)
Subject: ARM: dts: stm32f429: Boost perfs by remapping SDRAM Bank 1 to 0x0
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b2aa7f7741f511c6a1ea266d62d203662f121ea7;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

ARM: dts: stm32f429: Boost perfs by remapping SDRAM Bank 1 to 0x0

STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0,
by writing 0x4 to SYSCFG_MEMRMP register.

As mentionned in the reference manual (see chapter 9.3.1), the performance
gain is really interresting:
"In remap mode at address 0x0000 0000, the CPU can access the external
memory via ICode bus instead of System bus which boosts up the
performance."

These are the dhrystone results with and without the remap enabled:
Default (SDRAM in 0xc0000000):
---------------------------------
Microseconds for one run through Dhrystone:   31.8
Dhrystones per Second:                      31416.9

Remap (SDRAM in 0x0000000):
-----------------------------
Microseconds for one run through Dhrystone:   20.6
Dhrystones per Second:                      48520.1

This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL
board, and also set the dma-range property as the other masters than the M4
CPU still see SDRAM in 0xc0000000.

Note that the Discovery board cannot benefit from this feature, since the
SDRAM is connected to Bank 2.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
---

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index e3921d9b00c6..1ae57fad12d3 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -58,7 +58,7 @@
 	};
 
 	memory {
-		reg = <0xc0000000 0x2000000>;
+		reg = <0x00000000 0x2000000>;
 	};
 
 	aliases {
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index aa6c67d99921..35b2ab13b624 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -58,6 +58,8 @@
 	};
 
 	soc {
+		dma-ranges = <0xc0000000 0x0 0x10000000>;
+
 		timer2: timer@40000000 {
 			compatible = "st,stm32-timer";
 			reg = <0x40000000 0x400>;